Circuit for generating a demand-based gated clock

Details Circuit for generating a demand-based gated clock Circuit for generating a demand-based gated clock

1995-05-26

1997-01-28

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 39, H03K 19096

Patent

active

055981127

ABSTRACT:
A demand-based clocking circuit generates a demand-based gated clock signal. A latch circuit data input receives an enable signal. A clock input receives a first periodic input clock signal. A latch circuit data output provides a shifted enable signal that transitions from an inactive logic state to an active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state. The shifted enable signal transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the active to the inactive logic state. A logic circuit provides the gated clock signal such that the gated clock signal transitions from the inactive to the active logic state on the first transition of a second input clock signal from the first to the second logic state after the shifted enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the transition of the shifted enable signal from the active to the inactive logic state.

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