Circuit for generating a column switch enable signal of a memory

Details Circuit for generating a column switch enable signal of a memory Circuit for generating a column switch enable signal of a memory

1996-12-19

1998-06-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365222, G11C 700

Patent

active

057611360

ABSTRACT:
A circuit generates a column switch enable signal of a memory in response to an external column start signal in a normal memory access mode in order to prevent erroneous data from being output from the memory when an abnormal address signal is received. The circuit also generates, in a memory refresh mode, a column switch enable signal having a pulse width corresponding to the width of a sum signal which sums the number of memory accesses. This decreases the amount of current dissipated during the input and output of data. The circuit has a first unit for supplying a first control signal to control the shape of the column switch enable signal based upon an externally-provided column start signal in the normal mode, a second unit for supplying a second control signal to control the shape of the column switch enable signal based upon the externally-provided sum signal in a refresh mode, and a signal generating unit for generating the column switch enable signal based upon the first control signal or the second control signal respectively supplied from the first or second units.

REFERENCES:
patent: 4646272 (1987-02-01), Takasugi
patent: 4858197 (1989-08-01), Aono et al.
patent: 5349566 (1994-09-01), Merritt
patent: 5414672 (1995-05-01), Ozeki
patent: 5457659 (1995-10-01), Schaefer
patent: 5559752 (1996-09-01), Stephens, Jr.

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