Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-03-30
2003-05-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C365S227000
Reexamination Certificate
active
06563746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a low power consumption mode.
2. Description of the Related Art
In recent years, the cellular phone has been given not only a function to have a vocal communication but also a function to transmit character-string data or image data. Moreover, the cellular phone has been expected in the future to become a kind of information terminal (for example, a portable type personal computer) as the internet services are diversified. Thus, the information volume of data to be handled by the cellular phone has been drastically increasing. Conventionally, the cellular phone has employed as its work memory SRAMs having a memory capacity of about 4 Mbit. The work memory is a memory for retaining the necessary data during the operation of the cellular phone. It is obvious that the memory capacity of the work memory will be short in the future.
On the other hand, the transmission speed of the cellular phone has been heightening. The smaller the cellular phone becomes, the smaller the battery to be mounted becomes. Therefore, the work memory to be employed in the cellular phone is required to have a high speed, low power consumption and a large capacity. In the cellular phone serious price competitions, it is necessary to make the costs for parts as low as possible. Therefore, the work memory has to be at low price.
The conventional SRAMs as employed in the work memory are higher per bit in cost than DRAMs. The production number of SRAMs is smaller than that of the DRAMs so that it is difficult to lower its price. Moreover, there have never been developed SRAMs having a large memory capacity (for example, 64 Mbit).
In this situation, it has been considered to replace the SRAMs by flash memories and DRAMs in the work memory of the cellular phone.
The flash memory has a power consumption as low as several &mgr;W during a standby state but requires several &mgr;s to several tens &mgr;s for writing data. When the flash memory is employed as the work memory of the cellular phone, therefore, it is difficult to transmit/receive massive data at high speed. The flash memory performs the write operation at the unit of a sector so that it is not suitable for rewriting bit by bit image data such as the data of a moving image.
On the contrary, the DRAMs can execute both the read operation and the write operation within several tens ns and can process the data of the moving image easily. The power consumption during the standby state is higher than that of the flash memories. In the present DRAMs, the power consumption in the standby state is about 1 mW during a self-refresh mode for retaining written data and about 300 &mgr;W during a standby mode not required for retaining written data.
If the power consumption during the standby mode could be reduced to that of the flash memories, the DRAMs could be employed as the work memory of the cellular phone, but such circuit technology has never been proposed.
The power consumption of the DRAMs can be reduced to zero by stopping the power supply to the DRAMs. However, since the address terminals, the data terminals and the like of the DRAMs are connected with the terminals of other electronic parts through the wiring patterns on a circuit board, it is required to drastically change the system of the cellular phone (the pattern change of the circuit board, re-layout and so on) for the termination of the power supply to the DRAMs.
Besides, there has not been proposed a technology which realizes exit from the standby mode without the malfunction of an internal circuit after the power supply is terminated to stop the operation of the internal circuit during the standby mode.
Where the internal voltage to be used in the internal circuit is generated inside of the device, it has to be quickly returned to a predetermined voltage when a release is made from a standby mode (a low power consumption mode). However, this technique has never been proposed.
SUMMARY OF THE INVENTION
An object of the present invention is to enter the device into a low power consumption mode and exit the device from a low power consumption mode with reliability.
Another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during standby mode as compared with the conventional devices and a method of controlling the semiconductor memory device.
Still another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during a standby period as compared with the conventional devices and a method of controlling the semiconductor memory device.
Another object of the present invention is to easily enter a device into a low power consumption mode by a control signal from the exterior.
Another object of the present invention is to prevent the feedthrough current (or leak path) of an internal circuit during a low power consumption mode.
Still another object of the present invention is to easily enter the device into the low power consumption mode by employing an existing control signal.
Another object of the present invention is to easily enter the device into the low power consumption mode by a command input.
Another object of the present invention is to easily enter the device into the low power consumption mode by a dedicated control signal.
Another object of the invention is to quickly return from the low power consumption mode.
According to one aspect of the semiconductor memory device in the present invention, an internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. When the internal voltage generator is operated, a predetermined amount of electric power is consumed. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. The internal voltage is not to be generated due to the inactivation of the internal voltage generator so that the power consumption may be reduced. In response to the control signal from the exterior, therefore, it is possible to easily enter the device into the low power consumption mode.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a booster and the generation of a boost voltage to be supplied to a word line. During the low power consumption mode the booster steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a substrate voltage generator to stop the generation of a substrate voltage to be supplied to a substrate. During the low power consumption mode, the substrate voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of an internal supply voltage generator to stop the generation of an internal supply voltage to be supplied to a memory core. During the low power consumption mode, the internal supply voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a precharging voltage generator to stop the generation of a precharging voltage to be supplied to bit lines. During the low power consumption mode, the precharging voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semico
Fujioka Shin-ya
Kawakubo Tomohiro
Nishimura Koichi
Sato Kotoku
Arent Fox Kinter Plotkin & Kahn PLLC
Fujitsu Limited
Nelms David
Yoha Connie C.
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