Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-03-30
2001-03-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06198308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for adjusting the rate at which signal transitions occur. In particular, the present invention relates to buffer circuits providing faster switching. More particularly, the present invention relates to circuitry that dynamically adjusts the threshold potential at which signal transitions occur.
2. Description of the Prior Art
Input buffers are used to transfer electrical signals of desired amplitude and strength. Input buffers are used to ensure that those electrical signals are transferred as accurately and as quickly as possible. It is often the case, however, that when transmission rates increase, signal accuracy may suffer. In particular, it is well known that rapid signal transmission may be accompanied by signal bounce. That bounce is the noise or ringing associated with the undershoot and overshoot of a final steady state logic high or logic low signal that occurs in the transition between high and low. The difference in the potentials associated with a high signal and a low signal may be as small as 0.4V or as great as 5V. For Complementary Metal Oxide Semiconductor (CMOS) based logic, for example, a logic high corresponds to a nominal 5.0V potential (for a 5.0V power supply) and a nominal 3.3V potential (for a 3.3V power supply), while a logic low is essentially equivalent to ground (GND) or 0.0V.
The potentials associated with high and low signals described above are idealized values. In fact, highs and lows generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3V supply, a high signal may be supplied at 2.6V, for example, while a low signal may actually be associated with a 0.7V value. It can be seen then that dynamic noise margins are reduced with lower supply potentials, whereas the basic operational characteristics of the associated active devices remain substantially the same.
In that regard, it is to be noted that in most systems, there is a single threshold potential at which the low-to-high (L-to-H) or high-to-low (H-to-L) transitions occur. For most transistor-based devices, that value is typically about one-half of the supply potential, or Vcc/2. As the potentials of the power supplies used to power circuitry move closer to GND, the signal bounce mentioned above takes on greater importance. In particular, the initial oscillation around the ultimate steady state value that occurs when the transition between high and low is triggered may vary enough to generate a false logic signal. The noise swing may be enough to cause a low signal to transition to a high-signal potential and vice-versa, or it may be variable enough that the signal is not clearly at either a high potential or a low potential. Either situation is undesirable. For that reason, it is becoming increasingly important that the transitions between high and low signal occur with less noise than has been previously experienced.
Clearly, unexpected changes in logic values are not desirable. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the signal bounce that occurs with the rapid switching often creates reflections in transmission media, such as telephone transmission lines where reflections will cause signal errors. This is an increasingly important concern as dynamic noise margins are reduced.
To resolve this problem, it is important to enable “gentle” switching of buffer circuits so that signal noise, including signal undershoot and overshoot, is reduced. One technique for doing that is to slow the propagation of a switching signal through the circuitry. This slows the transmission of the signal and is therefore adverse to the goal of increasing signal transmissions. While the intentional slowing of signal propagation addresses the noise issue, it also reduces transmission rates. Of course, there are a number of other factors that cause increases in signal propagation delay. They can be related to the specifics of particular circuitry, the load associated with downstream devices, external conditions, and any number of other factors. However, it is of increasing interest to minimize signal propagation delays.
As noted, the rate at which a signal propagates through circuitry including, but not limited to input buffer circuitry, relates to the threshold potential at which transistors of the buffer are turned on and off. In general for Complementary Metal-Oxide-Semiconductor (CMOS) transistor sets, state switching occurs at about one-half the value of Vcc as earlier indicated. That is, in a L-to-H transition for example, a P-type MOS (PMOS) transistor of a CMOS inverter will turn on when an input signal is at a potential of about Vcc/2. At about the same time, the N-type MOS (NMOS) transistor of that inverter will switch off at that potential. Correspondingly, the PMOS transistor is designed to shut off at about Vcc/2 during a H-to-L transition, with the NMOS turning on at about that potential. Thus, in order to trigger a signal change, it is necessary to first reach this threshold potential in either direction. The faster that is done the more the signal propagation delay is reduced. However, that is preferably done with signal noise concerns also taken into account.
U.S. Pat. No. 5,736,826 issued to Hrassky discloses a circuit designed to regulate signal propagation through hysteresis. The Hrassky circuit includes two multiplexed buffers to develop a differential comparison of two input signals. The circuit provides for selection of the particular input signal path that includes sufficient hysteresis to resolve noise concerns. While hysteresis may minimize the effects of signal bounce by regulating signal propagation, it does so in a manner that slows that propagation. That result is undesirable as accurate signal transmission at reduced signal propagation rates becomes increasingly important.
Therefore, what is needed is a buffer circuit that enables signal propagation with minimal noise problems and at reduced delay rates. What is also needed is such a buffer circuit that can be tailored to provide a modification in the threshold potential value at which signal switching occurs. Further, what is needed is a buffer circuit that allows the user to tailor selection of a particular signal transmission pathway as a function of desired propagation delay values.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a buffer circuit that enables signal propagation with minimal noise problems and at reduced delay rates. It is also an object of the present invention to provide such a buffer circuit that can be tailored to modify the threshold potential value at which signal switching occurs. Another object of the present invention is to provide a buffer circuit that allows the user to tailor selection of a particular signal transmission pathway as a function of desired propagation delay values.
These and other objects are achieved in the present invention by creating a buffer having an input branch coupled to a logic circuit, a latch subcircuit, and a pair of pass gate sets. The input branch includes a pair of inverters tailored to have skewed threshold potentials at which switching occurs. Both inverters are coupled to an input node of the buffer circuit for receiving an incoming signal to be propagated to downstream circuitry coupled to the buffer's output node. For L-to-H signal inputs the first inverter is designed to switch at some potential less than Vcc/2 while the second inverter is designed to switch at some potential greate
Atwood Pierce
Caseiro Chris A.
Fairchild Semiconductor Corp.
Tokar Michael
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