Circuit for device isolation

Details Circuit for device isolation Circuit for device isolation

1998-04-01

2003-01-07

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S373000, C257S408000

Reexamination Certificate

active

06504211

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices, especially to MOSFET and related devices, and to the structure and formation of source/drain regions in such devices. More particularly, the present invention relates to structures for improved isolation of source/drain regions, particularly useful to isolate storage nodes in a DRAM device, and to methods for forming the same.
2. The Relevant Technology
FIG. 1
shows a cross section of some elements of a typical MOSFET type device. A substrate
12
is typically lightly doped P type, having consequently a positive space charge in the bulk or major part thereof. A gate
14
is separated from substrate
12
by a gate oxide
16
. Source/drain regions
18
,
20
have been formed in substrate
12
by doping substrate
12
with N-type dopant(s), resulting in a negative space charge within source/drain regions
18
,
20
. A field oxide isolation region
22
isolates individual electrically active areas of substrate
12
.
Certain of the electrical characteristics of a device such as that shown in
FIG. 1
, as employed in DRAM and similar applications, are illustrated in the circuit diagram of
FIG. 2. A
bit line
24
contacts one side of a transistor
28
corresponding to a source/drain region such as source/drain region
18
of
FIG. 1
, while a word line
26
contacts the gate of transistor
28
corresponding to a gate such as gate
14
of FIG.
1
. At the other side of transistor
28
is located a storage node N corresponding to a second source/drain region such as source/drain region
20
of
FIG. 1
, where an electrical charge may be stored to or retrieved from a capacitor
30
connected thereto. A junction between semiconductor regions having opposite space charges acts as a junction diode
32
between storage node N and
2
ground, reducing current leakage from capacitor
30
through storage node N to ground. This junction diode corresponds to the junction between source/drain region
20
and substrate
12
in FIG.
1
.
The junction between source/drain region
20
and substrate
12
, like essentially every diode, inherently leaks current. In DRAM devices and similar applications, a charge stored at capacitor
30
is typically used to represent a 1-bit, and a lack of charge a 0-bit. The stored charge (or lack thereof) is refreshed at regular intervals. The leakage across junction diode
32
must be small enough so that a charge stored in a capacitor connected to source/drain region
20
will not dissipate between refresh cycles.
As miniaturization of integrated circuits increases, the capacitance of a cell capacitor in a DRAM circuit tends to decrease, making smaller leakage desirable to maintain adequate charge between refresh cycles. If leakage is sufficiently small, the time between refresh cycles can even be increased, resulting in faster responding DRAM with less power consumption. Thus it is desirable to decrease the leakage from a source/drain region to a substrate, particularly a source/drain region functioning as a storage node in a DRAM or similar device.
SUMMARY AND OBJECTS OF THE INVENTION
An object of the present invention is to provide a method of reducing current leakage from a source/drain region to an associated substrate.
A further object of the present invention is to provide a source/drain region structure having decreased leakage to a substrate.
Still a further object of the present invention is to provide a method of forming a source/drain region structure having decreased leakage to a substrate.
Still a further object of the present invention is to provide a cell structure for DRAM and similar devices allowing a lower frequency of refresh cycles.
In accordance with the present invention, a source/drain region is formed in a substrate, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The forgoing source/drain region structure provides three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one.
Also in accordance with the present invention, the structure briefly described above may be formed by first implanting into a first region a first species, the implanting of the first species causing a space charge to arise in the first region opposite in polarity to a space charge in the major part of a substrate in which the source/drain region is formed. Second, a second species is implanted into a second region, the second region being enclosed from the major part of the substrate by the first region and extending under the gate of the associated gate stack. The implanting of the second species into the second region results in a space charge in the second region having a polarity opposite to the polarity of the space charge in the first region. Third, a third species is implanted into a third region, the third region extending to the source/drain contact area and enclosed from the first region and the major part of the substrate by the second region and extending laterally up to but preferably not significantly under the gate of the associated gate stack. The implanting of the third species into the third region results in the third region having a space charge opposite in polarity to the space charge in the second region.
The implanting of the first species and the implanting of the second species is preferably accomplished by an angled implant performed after the associated gate stack is formed, but before spacers are formed on the associated gate stack. The implanting of the third species is preferably performed by an angled implant after the formation of spacers enclosing the associated gate stack.
The above briefly described structure and method result in decreased current leakage from a source/drain contact area to substrate, allowing greater time between refresh cycles in a DRAM device in which the above structure and method are employed.


REFERENCES:
patent: 5366915 (1994-11-01), Kodama
patent: 5426326 (1995-06-01), Ohyu et al.
patent: 5532508 (1996-07-01), Kaneko et al.
patent: 5672533 (1997-09-01), Arima et al.
patent: 5763916 (1998-06-01), Gonzalez et al.

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