Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
Reexamination Certificate
1998-05-21
2001-02-27
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error detection for synchronization control
C714S811000, C713S503000
Reexamination Certificate
active
06195784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for receiving bits transmitted asynchronously, and more specifically to a reception error detection circuit.
2. Discussion of the Related Art
FIG. 1
schematically shows a circuit for receiving bits transmitted on an asynchronous signal Din. Signal Din is provided to a phase-locked loop (PLL)
10
to reconstruct a clock signal CKR, the period of which is in principle equal to the width of the bits of signal Din. Reconstructed clock CKR is used to sample asynchronous signal Din by means of a flip-flop
12
that provides the sampled bits on a synchronous signal Ds. Ideally, signal CKR is such that flip-flop
12
samples each bit of asynchronous signal Din at its center.
The accuracy of reconstructed clock CKR depends on several factors, especially on the regularity of the variation of asynchronous signal Din. Asynchronous signal Din is random, but it can often convey several consecutive bits at a same state, which causes a drift of phase-locked loop
10
towards a lower frequency. Further, parasitic pulses in asynchronous signal Din are likely to cause a drift of phase-locked loop
10
towards a higher frequency.
When the frequency of reconstructed clock CKR is not exactly set on the transmission rate of asynchronous signal Din, the circuit inevitably ends up making sampling errors.
FIG. 2
shows an example of a timing diagram of the signals of the circuit in
FIG. 1
, illustrating an error occurring when the frequency of reconstructed clock CKR is higher than the transmission rate of the bits on signal Din. For simplification, the signals have been shown in square form. In reality, these signals have smooth transitions. The switching and propagation delays of the flip-flops have also been neglected.
In this example, the successive bits transmitted on signal Din switch at each bit, and signal Din is sampled upon each rising edge of clock signal CKR.
Upon the first rising edge of clock CKR, a bit of signal Din, at 1, is sampled in ideal conditions, that is, substantially at its center. Signal Ds switches to 1 during this rising edge.
At a given time, two successive rising edges of clock CKR, here the fourth and fifth rising edges, occur within a same bit of signal Din. In other words, the same bit is sampled twice, which causes an error. In the example of
FIG. 2
, synchronous signal Ds conveys, at the time of occurrence of the error, two successive bits at 0.
When clock CKR is too slow, at a given time, two of its successive rising edges occur before and after a bit of signal Din, which causes the loss of this bit.
A conventional solution to detect errors in such a system is to compare the control signal of the oscillator of phase-locked loop
10
with high and low thresholds substantially equidistant from the nominal value of the control signal. When the control signal reaches one of these thresholds, this means that the phase-locked loop has drifted, and thus that the reconstructed clock is wrong. The thresholds must be sufficiently far apart from the nominal value so that they are not reached by variations of the control signal around the nominal value, due to noise and to manufacturing tolerances. Thus, the error detection reacts particularly slowly and, when it reacts, a significant unknown number of bits are erroneous.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a fast response error detection circuit.
Another object of the present invention is to provide such an error detection circuit which provides an indication for each erroneous bit.
These and other objects are achieved in a circuit for receiving bits transmitted on an asynchronous signal, including a circuit for providing a clock reconstructed from the asynchronous signal, this clock being used to sample the asynchronous signal to form a synchronous output signal, and a reception error detection circuit. The reception error detection circuit includes an edge detector providing a detection pulse for each edge of predetermined direction of the asynchronous signal; and an alarm circuit activating an alarm signal when an edge of predetermined direction of the synchronous signal occurs outside a detection pulse.
According to an embodiment of the present invention, the alarm circuit includes a flip-flop for sampling the detection pulses at edges of predetermined direction of the synchronous signal and activates the alarm signal when the output of the sampling flip-flop switches.
According to an embodiment of the present invention, the edge detector provides a detection pulse for each rising edge and a detection pulse for each falling edge of the asynchronous signal, the alarm circuit activating the alarm signal when a rising edge of the synchronous signal occurs outside a detection pulse corresponding to a rising edge of the asynchronous signal or when a falling edge of the synchronous signal occurs outside a pulse corresponding to a falling edge of the asynchronous signal.
According to an embodiment of the present invention, the edge detector includes a first flip-flop clocked from the asynchronous signal, receiving an active state on its data input, and providing detection pulses; and a second flip-flop clocked from the reconstructed clock receiving the detection pulses on its data input, and providing a reset signal for the first flip-flop.
According to an embodiment of the present invention, the second flip-flop is clocked by the complement of the reconstructed clock, the first flip-flop being directly clocked by the asynchronous signal to detect rising edges or by the complement of the asynchronous signal to detect falling edges.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4737971 (1988-04-01), Lanzafame et al.
patent: 4800340 (1989-01-01), Maimone et al.
patent: 4876701 (1989-10-01), Sanner
patent: 4935942 (1990-06-01), Hwang et al.
patent: 4984255 (1991-01-01), Davis et al.
patent: 5331669 (1994-07-01), Wang et al.
patent: 5463655 (1995-10-01), Llewellyn
patent: 5708381 (1998-01-01), Higashisaka
Galanthay Theodore E.
Morris James H.
SGA-Thomson Microelectronics S.A.
Tu Christine T.
Wolf Greenfield & Sacks P.C.
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