Circuit for detecting improper bus termination on a SCSI bus

Details Circuit for detecting improper bus termination on a SCSI bus Circuit for detecting improper bus termination on a SCSI bus

1998-09-24

2000-09-05

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710101, 326 30, G06F 1300, G01R 2700, H03K 1908

Patent

active

061157732

ABSTRACT:
A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.

REFERENCES:
patent: 3832575 (1974-08-01), Dasgupta et al.
patent: 5214670 (1993-05-01), Ballatore
patent: 5311081 (1994-05-01), Donaldson et al.
patent: 5559440 (1996-09-01), Lopresti et al.
patent: 5748910 (1998-05-01), Herrera
patent: 5821767 (1998-10-01), Osaka et al.

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