Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2007-08-09
2009-10-20
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S027000, C326S080000
Reexamination Certificate
active
07605608
ABSTRACT:
In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
REFERENCES:
patent: 3961326 (1976-06-01), Craven
patent: 4825099 (1989-04-01), Barton
patent: 4937477 (1990-06-01), Tsoi et al.
patent: 5028817 (1991-07-01), Patil
patent: 5128556 (1992-07-01), Hirakata
patent: 5539341 (1996-07-01), Kuo
patent: 5625360 (1997-04-01), Garrity et al.
patent: 5751186 (1998-05-01), Nakao et al.
patent: 5781026 (1998-07-01), Chow
patent: 5900741 (1999-05-01), Roohparvar
patent: 5909187 (1999-06-01), Ahuja
patent: 6100830 (2000-08-01), Dedic
patent: 6188244 (2001-02-01), Joo et al.
patent: 6339344 (2002-01-01), Sakata et al.
patent: 6407688 (2002-06-01), Greig
patent: 7023367 (2006-04-01), Manganaro
patent: 7034733 (2006-04-01), Dedic et al.
patent: 7355449 (2008-04-01), Tran et al.
patent: 7432741 (2008-10-01), Shumarayev
U.S. Appl. No. 11/836,584, filed Aug. 9, 2007, Rezzi et al.
U.S. Appl. No. 11/836,619, filed Aug. 9, 2007, Rezzi et al.
U.S. Appl. No. 11/836,628, filed Aug. 9, 2007, Rezzi et al.
U.S. Appl. No. 11/836,635, filed Aug. 9, 2007, Rezzi et al.
U.S. Appl. No. 11/846,292, filed Aug. 28, 2007, Rezzi et al.
Office Action in 11/836,619, dated Oct. 29, 2008.
Interview Summary in 11/836,619, dated Nov. 10, 2008.
Office Action in 11/836,635, dated Dec. 24, 2008.
Office Action for U.S. Appl. No. 11/836,635 dated May 21, 2009.
Notice of Allowance for U.S. Appl. No. 11/836,584.
Cesura Giovanni Antonio
Ghittori Nicola
Jamal Shafiq M.
Rezzi Francesco
Cho James H.
Hammond Crystal L
Marvell International Ltd.
LandOfFree
Circuit for converting a voltage range of a logic signal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for converting a voltage range of a logic signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for converting a voltage range of a logic signal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4066708