Circuit for conversion from CMOS voltage levels to shifted ECL v

Details Circuit for conversion from CMOS voltage levels to shifted ECL v Circuit for conversion from CMOS voltage levels to shifted ECL v

1993-10-18

1994-11-15

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 68, H03K 190175

Patent

active

053651278

ABSTRACT:
A CMOS level conversion circuit for converting voltage levels between CMOS levels and shifted ECL levels, where the shifted ECL levels are referenced to the VDD supply voltage of the CMOS circuit. The circuit contains a pFET connected between the VDD supply voltage and the output terminal and an nFET connected between the output terminal and circuit ground. The input signal is connected to the gate input of the nFET. A second pFET is connected in parallel to the nFET between the output terminal and ground. A bias voltage is supplied to the gate inputs of both pFETs, to cause the output terminal to have a shifted ECL logic one voltage when the gate to the nFET is low. The pFETs are fabricated within the integrated circuit to be located very close to each other to compensate for variations in the CMOS integrated circuit manufacturing process.

REFERENCES:
patent: 4791322 (1988-12-01), Graham
patent: 4808852 (1989-02-01), Kousaka
patent: 4998028 (1991-03-01), Chappell
patent: 5043605 (1991-08-01), Gabara

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