Circuit for controlling writing data into memory and allowing co

Details Circuit for controlling writing data into memory and allowing co Circuit for controlling writing data into memory and allowing co

1997-08-12

2000-09-12

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711154, 711106, 36518901, 365195, G06F 1200

Patent

active

061192112

ABSTRACT:
There is provided a circuit for controlling writing data into an address of a memory, the data and address being transmitted from a central processing unit, the circuit (a) latching address and data transmitted from the central processing unit, (b) storing a first signal transmitted from the central processing unit, (c) writing latched data into a latched address of the memory by a second signal associated with the first signal, and (d) invalidating the second signal after a period of time necessary for writing data into the address has passed. The above mentioned circuit makes sure that writing data into a memory can be completed without destruction of the data, even if a reset factor is generated while data is being written into a memory. In addition, reset timing for an entire device in which the above mentioned circuit is contained is not out of phase, ensuring prevention of malfunction of the device.

REFERENCES:
patent: 4962487 (1990-10-01), Suzuki
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patent: 5351216 (1994-09-01), Salt et al.
patent: 5457660 (1995-10-01), Ito
patent: 5574920 (1996-11-01), Parry
patent: 5748560 (1998-05-01), Sawada
patent: 5768190 (1998-06-01), Tanaka et al.
patent: 5825691 (1998-10-01), McClure
patent: 5835706 (1998-11-01), Hikichi et al.

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