Circuit for controlling sequential access to SDRAM

Details Circuit for controlling sequential access to SDRAM Circuit for controlling sequential access to SDRAM

2005-02-22

2005-02-22

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S026000, C710S035000, C710S308000, C711S105000, C711S152000

Reexamination Certificate

active

06859848

ABSTRACT:
A DMA controller arbitrates and selects a DMA control information signal received from at least one of a plurality of DMA request blocks and accesses an SDRAM on the basis of the selected DMA control information signal. In the DMA controller, an SDRAM controller detects using a detector the number of possible sequential accesses on the basis of a DMA start address signal, compares using a comparator this number of possible sequential accesses with the burst DMA request number designated by a BSTNUM signal, selects not larger one of the two numbers, and sets the number of sequential DMAs to be actually executed to the selected number. Accordingly, with a simple configuration, sequential access is made possible starting from an arbitrary address.

REFERENCES:
patent: 6144460 (2000-11-01), Omo et al.
patent: 6366989 (2002-04-01), Keskar et al.
patent: 6622203 (2003-09-01), Simmons et al.
patent: 2000215155 (2000-08-01), None

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