Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2009-07-10
2010-12-28
Chang, Daniel D (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S062000, C365S189060
Reexamination Certificate
active
07859299
ABSTRACT:
A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.
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Gay James G.
Greaves Carlos A.
Chang Daniel D
Freescale Semiconductor Inc.
Hill Susan C.
King Robert L.
Vo Kim-Marie
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