Circuit for controlling an enabling time of an internal...

Details Circuit for controlling an enabling time of an internal... Circuit for controlling an enabling time of an internal...

2011-03-08

2011-03-08

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S193000, C365S189050, C365S233100

Reissue Patent

active

RE042202

ABSTRACT:
Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.

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