Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-12-16
2004-09-21
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000
Reexamination Certificate
active
06795354
ABSTRACT:
This application claims priority from Korean Patent Application No. 2001-81254, filed on Dec. 19, 2001, the contents of which are incorporated herein by this reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit for controlling an AC-timing parameter of a semiconductor memory device by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory device operation-timing (also referred to as AC-timing) parameters define a specific operating time or a time interval between specific operations, and the permitted limit of the operation timing is stipulated so as to guarantee the normal operation of a semiconductor memory device.
In general, the specified value for a semiconductor memory device AC-timing parameter is defined as a multiple of a predetermined reference time or a cycling time of a reference clock signal. The broader the permitted limit of the value of the specification of the AC-timing parameter, the greater guarantee for a better quality semiconductor memory device. As the permitted limit of the specified value for the AC-timing parameter is increased, however, circuit design becomes more difficult as it is difficult to obtain the same operational characteristics within the permitted limit.
In a conventional semiconductor memory device, the problem is resolved by mounting a selective fuse or a selective metal, or by applying a specific mode register set (MRS) when designing circuitry. In the case of mounting a selective metal, a separate mask is required, and thus the manufacturing cost of the mask increases. In the case of mounting a selective fuse, a space for mounting the fuse must be obtained, and thus the chip size increases. Also, a fuse cutting procedure must be included seperately, and thus manufacturing cost and time increase.
When applying a MRS, a circuit for applying a MRS must be included, and thus the chip size increases. A separate procedure such as fuse cutting is unnecessary, however, and even a finished product can be modified.
Where the AC-timing parameter is varied and there is a need to reflect the variation when applying a MRS, however, a procedure for programming a MRS must be separately performed. Thus, it is difficult to maintain the same semiconductor memory device operational characteristics and the performance of the semiconductor memory device is lowered.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a circuit for controlling a semiconductor memory device AC-timing parameter by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.
It is a second object of the present invention to provide a method for controlling a semiconductor memory device AC-timing parameter by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.
It is a third object of the present invention to provide a circuit for recognizing a cycle of a semiconductor memory device reference clock signal and controlling the operation of the semiconductor memory device.
Accordingly, to achieve the first object, there is provided a circuit for controlling a semiconductor memory device AC-timing parameter. The circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion.
The delay-time-defining portion receives consecutive input signals and generates first through n-th (n is a natural number) delay signals in which the input signals are delayed by corresponding predetermined delay times.
The comparing portion receives the input signals and the first through n-th delay signals and generates first through n-th comparison pulse signals, each having an active section for a corresponding predetermined duration.
The controlling portion receives the input signals and the first through n-th comparison pulse signals, compares the input signals with the first through n-th comparison pulse signals, and generates first through n-th operation control signals for controlling a semiconductor memory device AC timing parameter.
Here, the input signals are semiconductor memory device clock signals or commands.
It is preferable that the delay-time-defining portion includes a first delay device for generating the first delay signal by receiving the input signals and by delaying the input signals by a predetermined delay time, a second delay device for generating the second delay signal by receiving the first delay signal and by delaying the first delay signal by a predetermined delay time, and an n-th delay device for generating the n-th delay signal by receiving an (n−1)-th delay signal and by delaying the (n−1)-th delay signal by a predetermined delay time.
It is also preferable that the comparing portion include first through n-th comparing means, which receive the input signals and the corresponding first through n-th delay signals, respectively, and generate the first through n-th comparison pulse signals, each having an active section for a predetermined duration.
It is also preferable that the controlling portion includes first through n-th operation-controlling parts, which receive the input signals and the corresponding first through n-th comparison pulse signals, respectively, compare times of active sections of the input signals with times of active sections of the corresponding first through n-th comparison pulse signals, and generate first through n-th operation control signals.
It is also preferable that the circuit further includes an operation-determining portion, which receives the input signals and an operation-enabling signal, and determines whether or not operation input signals are transferred to the delay-time-defining portion.
To achieve the second object, there is provided a method for controlling a semiconductor memory device AC timing parameter by recognizing a variation in the AC timing parameter and controlling the operation of the semiconductor memory device. The method includes: (a) receiving consecutive input signals and generating first through n-th (n is a natural number) delay signals in which the input signals are delayed by corresponding predetermined delay times; (b) receiving the input signals and the first through n-th delay signals and generating first through n-th comparison pulse signals, each having an active section for a predetermined duration; and (c) receiving the input signals and the first through n-th comparison pulse signals, comparing the input signals with the first through n-th comparison pulse signals and generating first through n-th operation control signals for controlling an AC-timing parameter of the semiconductor memory device. Here, the input signals are semiconductor memory device clock signals or commands.
It is preferable that step (a) includes: (a1) generating the first delay signal by receiving the input signals and by delaying the input signals by a predetermined delay time; (a2) generating the second delay signal by receiving the first delay signal and delaying the first delay signal by a predetermined delay time; and (a3) generating the n-th delay signal by receiving an (n−1)-th delay signal and by delaying the (n−1)-th delay signal by a predetermined delay time.
To achieve the third object, there is provided a circuit for recognizing a cycle of a reference clock signal. The circuit includes an operation-determining portion, a delay-time-defining portion, a comparing portion, and a controlling portion.
The operation-determining portion receives consecutive input signals and an operation-enabling signal and generates an operation-determining signal for controlling the operation of the controlling portion.
The delay-time-defining portion receives the input signals and generates first and second delay signals, in which the input signals are delayed by corresponding predetermined delay ti
Cho Jeong-Hyeon
Kim Byung-Chul
Le Thong
Marger Johnson & McCollom. P.C.
Samsung Electronic Co. Ltd.
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