Circuit for comparing two N-digit binary data words

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C714S817000, C326S052000, C326S104000

Reexamination Certificate

active

07818656

ABSTRACT:
The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function.

REFERENCES:
patent: 2004/0066213 (2004-04-01), Kwak et al.
patent: 2006/0022864 (2006-02-01), Lee
patent: 2007/0063742 (2007-03-01), Janssen et al.
patent: 2008/0059853 (2008-03-01), Ushikubo
patent: WO 2006/099822 (2006-09-01), None
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Matakias, et al., “Ultra Fast and Low Cost Parallel Two-rail Code Checker Targeting High Fan-in Applications,” VLSI, Proceedings of IEEE Computer Society Annual Symposium, IEEE Comp. Soc, Feb. 2004, 293-296.
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Saposhnikov, et al., “Necessary and Sufficient conditions for the Existence of Totally Self-Checking Circuits,” IOLTS, Proceedings of the VLSI Test Symposium, 10th IEEE International, Jul., 2004, 25-30.
Tarnick, “Controllable Self-Checking Checkers for Conditional Concurrent Checking,” Proceedings of VLSI Test Symposium, 12th IEEE Comp. Soc., Apr. 1994, 144-150.

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