Circuit for bit alignment in high speed multichannel data...

Details Circuit for bit alignment in high speed multichannel data... Circuit for bit alignment in high speed multichannel data...

2004-06-15

2009-10-20

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S224000, C375S226000, C375S354000

Reexamination Certificate

active

07606341

ABSTRACT:
An alignment circuit is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on a data bus wherein said data bits are aligned with respect to said reference clock signal but misaligned with respect to each other. It first comprises a plurality of n aligners. Each aligner is coupled to said reference clock and a pair of said data bits, referred to as primary bits, one data bit (bit_tdat(i)) having the rank (i) in a determined set and the other being the corresponding data bit (bit_tdat(i+n)) having the rank (i+n) in the set. Each aligner comprises first, second and third shifting means for shifting said primary data bits to respectively generate respective data bits delayed of one, two and two and half cycles and a multiplexor receiving said primary and delayed data bits under the control of three control signals of a first type (recal(i), realign0(i) and realign1(i)) to generate a pair of aligned data bits (tdat_desk(i) & tdat_desk(i+n)).

REFERENCES:
patent: 4879731 (1989-11-01), Brush
patent: 5727021 (1998-03-01), Truebenbach
patent: 6065127 (2000-05-01), Aizenberg et al.
patent: 6654824 (2003-11-01), Vila et al.
patent: 7035368 (2006-04-01), Pickering et al.
patent: 7054331 (2006-05-01), Susnow et al.
patent: 2003/0074609 (2003-04-01), Koyanagi et al.
patent: 1028369 (2000-08-01), None

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