Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-11-26
2004-09-28
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S126000, C326S127000
Reexamination Certificate
active
06798249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to current mode logic circuits, and more particularly, to a method and circuit for resetting current mode logic circuit elements that have a memory and/or initial state.
2. Related Art
Current mode logic (CML) is widely used to build high speed logic blocks, such as frequency dividers in PLLs and high speed serial link transceiver circuits. CML logic can operate two to three times faster than CMOS logic. For frequency dividers and counters, there is often a need to implement a reset to enable initialization of a defined state. In CMOS logic, this is done by using the resetable flip flops, which are typically implemented by having pull-up or pull-down transistors enabled in the reset state. Since CMOS logic is a complementary-type logic, where one path is turned ON and the other OFF, it is straightforward to use pull-up, pull-down and pass switch transistors to implement the reset. In CML, latches are realized using biased differential transistor pairs and crossover switches, and, unlike CMOS latches, speed and bias requirements do not easily allow a reset to be done by using pass transistors switches with pull-ups and pull-downs. A reset method commonly used in CML is described below.
In conventional art, which is illustrated by a divide-by-N circuit of
FIGS. 1-7
, a multiplexer
101
provides the initial state of the divide-by-N, and the reset mechanism is done sequentially from the input (vip, vin) to the output (vop, von). This is illustrated in
FIGS. 1-7
. The conventional CML divide-by-N circuit with an asynchronous reset shown in
FIG. 1
consists of three blocks:
N CML flip flops
103
A-
103
N are connected in series. Each CML flip flop
103
(illustrated in detail in
FIG. 2
) has two series-connected latches
201
A,
201
B and each latch
201
A,
201
B (illustrated in detail in
FIG. 3
) has NMOS differential transistor pair M
301
, M
302
, NMOS cross-coupled transistor pair M
303
, M
304
, NMOS transistor switches M
305
, M
306
, NMOS current source M
307
and resistors R
301
, R
302
.
CML combination logic
102
(illustrated in detail in FIG.
4
), includes NAND, NOR and MUX gates, and sets a duty cycle of divide-by-N circuit output.
CML multiplexer
101
(see
FIG. 5
) has NMOS differential transistor pairs M
501
-M
502
, M
503
-M
504
, NMOS transistor switches M
505
, M
506
, NMOS current source M
507
and resistors R
501
, R
502
. Multiplexer
101
with one input connected to (VSS, VDD) provides the initial state and isolates the unknown input signal disturbing the reset process when reset is positive.
FIG. 2
shows a structure of CML flip flop
103
. As shown in
FIG. 2
, CML flip flop
103
includes two CML latches
201
A,
201
B connected in series. CML latch
201
A has inputs (vip, vin), and outputs (vop, von) which are inputted into corresponding inputs (vip, vin) of the second CML latch
201
B. Both latches
201
A,
201
B have common clock inputs (clk, clkn).
FIG. 3
shows a structure of a CML latch
201
of FIG.
2
. As shown in
FIG. 3
, CML latch
201
has a differential transistor pair M
301
, M
302
, whose gates are driven by (vip, vin) respectively. CML latch
201
also has an NMOS cross coupled transistor pair M
303
, M
304
. Drains of transistors M
301
, M
302
, M
303
and M
304
are tied to VDD through pull-up resistors R
301
, R
302
. Sources of the differential transistor pair M
301
, M
302
are tied to a switch transistor M
305
, whose gate is driven by clock input clkn. Sources of cross-coupled transistor pair M
303
, M
304
are tied to a drain of transistor switch M
306
, whose gate is driven by clock input clk. Current source transistor M
307
, whose gate is biased by voltage vb, supplies current to sources of switch transistors M
305
, M
306
. Latch
201
produces outputs (vop, von) as shown in FIG.
3
.
FIG. 4
shows a circuit diagram of CML combination logic
102
of FIG.
1
. As shown in
FIG. 4
, CML combination logic
102
includes four differential transistor pairs (M
401
, M
402
), (M
403
, M
404
), (M
405
, M
406
), (M
407
, M
408
), and (M
409
, M
410
) forming NAND and MUX gates. Switches M
411
, M
412
, and M
413
are connected to sources of respective differential transistor pairs, as shown in FIG.
4
. Tail current source transistors M
414
and M
415
supply current to the differential transistor pairs. Power supply voltage VDD is provided through pull-up resistors R
401
-R
402
, R
403
-R
404
, and outputs (vop, von) are connected to the pull-up resistors R
403
-R
404
as shown in FIG.
4
. The “sel” signal is an internal signal of CML combination logic
102
, and can be connected to power or ground. It sets the first output of (vop, von) to be logic “1” or “0” for duty cycle setting after reset and the “sel” setting is up to the user. Note that it does not affect the reset operation.
FIG. 5
illustrates the circuit diagram of CML multiplexer
101
. As shown in
FIG. 5
, CML multiplexer
101
includes two differential transistor pairs (M
501
, M
502
) and (M
503
, M
504
). Tail current source transistor M
507
supplies current to sources of the differential transistor pairs (M
501
, M
502
) and (M
503
, M
504
) through switch transistors M
505
, M
506
. Switch transistors M
505
, M
506
are driven by a reset and resetn (inverted reset) signal, respectively. Drains of differential transistor pairs (M
501
, M
502
), (M
503
, M
504
) are connected to the supply voltage VDD through pull-up resistors R
501
, R
502
, respectively, and to outputs (vop, von), respectively, as shown in FIG.
5
.
To understand the reset operation of divide-by-N circuit, a reset of divide-by-2 is shown in FIG.
6
and is explained using the timing diagram of FIG.
7
. First, the input (VSS, VDD) of multiplexer
101
is selected by reset. Second, the output (VSS, VDD) of multiplexer
101
is asserted at the input (vip, vin) of CML flip flop
103
, and is read by the NMOS differential transistor pair M
301
, M
302
of first CML latch
201
A at a negative clock (clk) period (clk=LOW). Third, the output (VSS, VDD) of first CML latch
201
A is held by NMOS cross-coupled transistor pair M
303
, M
304
of first CML latch
201
A of CML flip flop
103
, and is read by the NMOS differential transistor pair M
301
, M
302
of second CML latch
201
B of CML flip flop
103
to the output (VSS, VDD) at the positive clk period (clk=HIGH). Fourth, the output (VSS, VDD) is held by NMOS cross-coupled transistor pair M
303
, M
304
of second CML latch
201
B at the negative elk period (clk=LOW). As a result, the output of CML flip flop
103
is reset to the initial state (VSS, VDD) at the second negative elk period (clk=LOW).
Since the conventional circuit resets (vip, vin), (qop, qon) and (vop, von) sequentially, its minimum reset duration must take slightly more than one clock period. For convenience, assume that one clock period is required for reset. Thus, the reset operation of a conventional divide-by-N is such that all the outputs of CML flip flops
103
are reset to the defined value (VSS, VDD) at one clock period.
The disadvantages of the conventional CML divide-by-N with asynchronous reset are as follows:
In a convention reset circuit, multiplexer
101
is used to define an initial state of the circuit. Multiplexer
101
introduces a delay when it is not being used (i.e. when no reset is applied to the circuit), however, the multiplexer is always in the signal path, introducing a delay. CML multiplexer
101
with a propagation delay (t
d
) requires the minimum pulse width to be t
d
+t
setup
+t
hold
. For example, t
d
is 40 ns in the 1.2V 3.125 GHz Serdes standard, and it is 12.5% of full speed clock 3.125 GHz. As operational speed increases, the propagation delay t
d
becomes a bottleneck.
Extra current consumption I
MUX
is needed for multiplexer
101
that provides the initial state. There is a dependence between the extra current consumption I
MUX
and the reset duration. If each CML flip flop
103
has its own multiplexer
101
, then the
Ho David
Lee Wee Teck
Low Khim Leng
Wong Tak Ying
Broadcom Corporation
Sterne Kessler Goldstein & Fox PLLC
Tan Vibol
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