Circuit for and method of reading data in an asynchronous...

Static information storage and retrieval – Read/write circuit – Serial read/write

Reexamination Certificate

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C365S230020, C365S230080, C711S156000, C711S211000

Reexamination Certificate

active

07436726

ABSTRACT:
A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write address count, while a read address counter stores a read address count. Finally, a backup circuit receives a read address associated with data read from a slot of the plurality of slots. According to an alternate embodiment, a most significant bit circuit is coupled to an output of the write address counter for setting the most significant bit of the write address. A method of reading data stored in an asynchronous FIFO memory of an integrated circuit is also disclosed.

REFERENCES:
patent: 6434642 (2002-08-01), Camilleri et al.
patent: 6961280 (2005-11-01), Pan et al.
Xilinx, Inc.; DS261; Product Overview; “PCI-X/PCI HalfBridge Reference Design for Virtex-II Pro, Virtex-II, and Vertex-E FPGAs”; (v1.0) Jun. 23, 2003; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-11.

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