Circuit for and method of generating a delay in an...

Details Circuit for and method of generating a delay in an... Circuit for and method of generating a delay in an...

2006-08-30

2008-12-23

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C327S161000

Reexamination Certificate

active

07468616

ABSTRACT:
A circuit for generating a delayed output in an input/output port of a device adapted to implement circuits operating on a range of voltages is disclosed. The circuit comprises a first terminal of a delay stage of said input/output port coupled to receive a signal to be output by the circuit; a first pass gate coupled to the first terminal; a capacitor having a first terminal coupled to the output of the first pass gate and a second terminal coupled to ground; a second pass gate coupled to the first terminal of the capacitor; and a second terminal of said delay stage of said input/output port coupled to the second pass gate and outputting a delayed signal based upon the second pass gate. A method of generating a delayed output in an input/output stage of a device adapted to implement circuits operating on a range of voltages is also disclosed.

REFERENCES:
patent: 4458165 (1984-07-01), Jackson
patent: 4606584 (1986-08-01), Kowal et al.
patent: 5365204 (1994-11-01), Angiulli et al.
patent: 5812595 (1998-09-01), Jandu
patent: 2002/0175738 (2002-11-01), Cyrusian
patent: 2004/0004239 (2004-01-01), Madurawe

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