Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2006-09-12
2006-09-12
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S617000, C438S665000, C438S670000
Reexamination Certificate
active
07105384
ABSTRACT:
A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns21are removed using plasma to thereby improve the adhesion of conductive patterns21to a sealing resin28. By selective etching of a conductive foil10, separation grooves11are formed, thereby forming conductive patterns21. A semiconductor element22A and other circuit elements are mounted onto desired locations of conductive patterns21and electrically connected with conductive patterns21. By irradiating plasma onto conductive foil10from above, contaminants attached to the surfaces of separation grooves11are removed.
REFERENCES:
patent: 3541379 (1970-11-01), Holden
patent: 5635671 (1997-06-01), Freyman et al.
patent: 5675177 (1997-10-01), Abys et al.
patent: 5807787 (1998-09-01), Fu et al.
patent: 5909633 (1999-06-01), Haji et al.
patent: 6074895 (2000-06-01), Dery et al.
patent: 6083775 (2000-07-01), Huang et al.
patent: 6096649 (2000-08-01), Jang
patent: 6338980 (2002-01-01), Satoh
patent: 6383893 (2002-05-01), Begle et al.
patent: 6406991 (2002-06-01), Sugihara
patent: 6512295 (2003-01-01), Gaynes et al.
patent: 6528879 (2003-03-01), Sakamoto et al.
patent: 6596559 (2003-07-01), Kodnani et al.
patent: 6602803 (2003-08-01), Yew et al.
patent: 6689641 (2004-02-01), Ohta et al.
patent: 6713376 (2004-03-01), Sugihara
patent: 6889428 (2005-05-01), Igarashi et al.
patent: 2002/0106831 (2002-08-01), Tago et al.
patent: 2004/0006869 (2004-01-01), Igarashi et al.
patent: 2004/0152234 (2004-08-01), Usui et al.
patent: 2004/0234703 (2004-11-01), Frautschi
patent: 10-242097 (1998-09-01), None
patent: 10-270476 (1998-10-01), None
patent: 2002-076246 (2002-03-01), None
patent: 2002-110721 (2002-04-01), None
patent: 2002-280488 (2002-09-01), None
Igarashi Yusuke
Mizuhara Hideki
Sakamoto Noriaki
Usui Ryosuke
Brewster William M.
Fish & Richardson P.C.
Kanto Sanyo Semiconductors Co., Ltd.
Sanyo Electric Co. Ltd
LandOfFree
Circuit device manufacturing method including mounting... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit device manufacturing method including mounting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit device manufacturing method including mounting... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3557796