Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-09
2001-10-16
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S111000
Reexamination Certificate
active
06303964
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuits, and, more particularly, to the protection against electrostatic discharge in integrated circuits.
BACKGROUND OF THE INVENTION
Damage from electrostatic discharge (ESD) represents a significant cause of failure, with today's integrated circuits, especially in view of the continual trend of integrated circuits toward submicron physical dimensions. From the electrical standpoint, an ESD event occurs upon one or more of an integrated circuit terminals coming in contact with an object which is charged statically to a high voltage (which may be on an order of thousands of Volts). Upon such a contact, an integrated circuit would discharge the charged object through its active devices and DC paths. If the amount of the charge is too large, however, the density of the discharge current can damage the integrated circuit to the point of impairing its operability, or making it prone to fail later. Damage from ESD becomes, therefore, a cause of losses in production output as well as of decreased reliability in use.
It is common practice in the industry to provide integrated circuits individually with ESD protection devices connected to the circuit external pins. ESD protectors are designed to provide a current path of sufficient capacity to safely discharge a charge applied thereto by a charged object when an ESD event occurs, but without inhibiting the functionality of the integrated circuit in normal operation. The addition of ESD protectors unavoidably involves parasitic effects which lower the circuit performance. In such cases as when series resistors are used, ESD protectors directly introduce additional delay in the electrical performance. Consequently, a desirable objective of ESD protection devices should be to provide a high capacity current path which can be readily brought to act during an ESD event, but never during normal operation, and has minimal effects on the circuit performance.
One example of a conventional ESD protection device for bipolar integrated circuits is described in Avery, “Using SCR's as Transient Protection Structures in Integrated Circuits”,
Electrical Overstress/Electrostatic Discharge Symposium Proceedings
, (IIT Research Institute, 1983), pages 177-180. The protection device described therein is a vertical SCR (Silicon Controlled Rectifier). As is known, SCRs are capable of conveying relatively large amounts of current with relatively small resistance, especially if arranged to operate in their snap-back or “negative resistance” state.
In this specific field, a phenomenon associated with the turning on of a parasitic SCR structure, e.g. of PNPN or BJT type, is known as “latch-up” and causes an uncontrolled flow of current between two regions of a semiconductor integrated circuit. These regions may be a P+/Nwell (or P+/Nepi) junction connected to a supply voltage reference Vdd, and an N+/Pwell (or Nepi/Pwell) junction connected to a second voltage reference such as ground, respectively. The effect is regenerative and the latch-up cannot be suppressed by removing its cause, but only by cutting off the supply to the device.
As previously mentioned, electronic devices integrated in a semiconductor can be accessed from outside through contact pins, and the pins which are most affected by the latch-up phenomenon are the digital signal input and output pins. This is due to the most common cause of latch-up being a voltage discharge or spike that brings the pin affected by the phenomenon to a lower potential than the ground value, or a higher potential than the supply voltage Vdd.
Known are, in this respect, ESD protection structures adapted to protect the pins wherewith they are associated by either a conduction path triggering the latch-up phenomenon, a voltage pulse below the ground value, or a voltage pulse above the supply value. On this account, certain auxiliary barriers are added to the ESD protectors in order to reduce the triggering threshold of the parasitic SCR structure to a minimum.
The most efficient ESD protection structure currently provided by the state of the art, and commonly used for protecting low-voltage pins against electrostatic discharge of positive and negative signs, is illustrated by FIG.
1
. This structure basically includes an active limiting element PD which mostly comprises a lateral bipolar transistor of the NPN type or a base-emitter transistor; and a resistor R connected in series between the input/output pin (I/O) and a circuit to be protected. This P-type resistor is usually formed in a pocket or well of the N conductivity type connected to the pin. Shown schematically in the accompanying
FIG. 2
is a detailed view of the physical construction of an ESD protector with a lateral NPN transistor.
On the other hand,
FIG. 3
schematically shows a detailed view of the physical construction of an ESD protector with a base-emitter transistor, that is a transistor connected in a diode configuration and having its base and emitter terminals connected together. The circuit device of
FIG. 1
has applications to both the protection of input pins, with the resistor R being in the 2 to 5 k &OHgr;W range, and the protection of output pins, with the resistor R being less than a few hundred Ohms and sometimes zero Ohms.
FIG. 4
schematically shows the construction of the ESD protector of
FIG. 1
, comprising a protection transistor of the base-emitter transistor type and a resistor of the P conductivity type formed of an epitaxial N pocket connected to the pin to be protected. As previously mentioned, the peculiar construction of the active protection element PD and the pocket bias of R make this type of protection highly prone on latch-up.
However, there is no alternative solution currently available whereby the pocket of the resistor R can be biased such that the protector will be at one time efficient and free from parasitic paths in any possible applications. In fact, where a lateral transistor is provided, the parasitic SCR structure would be triggered on by a negative voltage discharge driving the resistor and the protector pockets to less than ground potential However, this arrangement would be immune to positive voltage discharge.
In addition, where the circuit to be protected is, for example, a CMOS buffer stage, the resistor R could be omitted, so that the parasitic SCR structure would be triggered on by both a negative voltage discharge, as in the previous instance, and a positive voltage discharge turning on a diode intrinsic to a P-channel transistor incorporated to the buffer stage to be protected.
SUMMARY OF THE INVENTION
An object of this invention is to provide a circuit device for ESD protection, which exhibits such structural and functional features as to be immune to the latch-up phenomenon, regardless of the type of the circuit to be protected. The device of this invention should also be suitable to protect digital or low voltage integrated circuit pins.
Another object of the invention is to provide a protection device structure based on the base-emitter transistor but having a series resistor formed by an extension of the collector region functioning as the transistor emitter and being diffused directly into the transistor base pocket.
More particularly, but not exclusively, the invention is directed to a protection device against electrostatic discharge which is immune to the latch-up phenomenon that usually affects conventional protection structures. The protection device is of a type integrated in a portion of a semiconductor integrated circuit, and includes an active limiting element and a resistor. The resistor is connected in series between a terminal of the active element, in turn connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected.
In this way, no problems from latch-up triggering will arise, since the terminal which is connected to the integrated circuit pin is led to a diffused region inside the base region of the protection transistor
REFERENCES
Pulvirenti Francesco
Ravanelli Enrico
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Meier Stephen D.
STMicroelectronics S.r.l.
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