Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-03-16
2003-04-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S678000, C257S690000, C257S692000, C257S698000, C257S774000
Reexamination Certificate
active
06545364
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of the Invention
The present invention relates to a circuit device and a method of manufacturing the circuit device, and particularly to a thin type circuit device and a manufacturing method of the circuit device which eliminates the need of a support substrate.
2. Description of the Related Art
Conventionally, the circuit device that is set on the electronic equipment is demanded to be smaller, thinner, and lighter, so that it can be employed in the portable telephones or the portable computers.
For example, the semiconductor devices as the circuit device are typically of the package type which is conventionally sealed by normal transfer molding. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.
29
.
This package type semiconductor device has a semiconductor chip
2
covered with a resin layer
3
, and a lead terminal
4
for outside connection derived from a side portion of this resin layer
3
.
However, this package type semiconductor device
1
with the lead terminal
4
extending out of the side face of the resin layer
3
was too large in whole size to satisfy the requirements of smaller, thinner and lighter constitution.
Therefore, the companies have developed various structures to realize the smaller, thinner and lighter semiconductor devices, and recently, what is called a CSP (Chip Size Package) has been developed, including a wafer scale CSP as large as the chip size or a CSP slightly larger than the chip size.
FIG. 30
shows a CSP
6
that uses a glass epoxy substrate
5
as the support substrate and is slightly larger than the chip size. Herein, a transistor chip T is mounted on the glass epoxy substrate
5
.
A first electrode
7
, a second electrode
8
, and a die pad
9
are formed on the surface of this glass epoxy substrate
5
, and a first back electrode
10
and a second back electrode
11
are formed on a back surface thereof. And the first electrode
7
and the first back electrode
10
, as well as the second electrode
8
and the second back electrode
11
are electrically connected via a through hole TH. Also, the bare transistor chip T is fixed on the die pad
9
, in which an emitter electrode of the transistor is connected with the first electrode
7
via a bonding wire
12
, and a base electrode of the transistor is connected with the second electrode
8
via the bonding wire
12
. Further, a resin layer
13
is provided on the glass epoxy substrate
5
to cover the transistor chip T.
The CSP
6
employs the glass epoxy substrate
5
, but has a simple structure extending from the chip T to the back electrodes
10
,
11
for outside connection, unlike the wafer scale CSP, with a merit of low manufacturing costs.
The CSP
6
is mounted on the printed circuit board PS, as shown in FIG.
29
. The printed circuit board PS is provided with the electrodes and interconnects making up an electrical circuit, to which the CSP
6
, the package type semiconductor device
1
, a chip resistor CR and a chip condenser CC are electrically connected and fixed.
A circuit constituted by this printed circuit board is installed on various sets.
Referring now to
FIGS. 31 and 32
, a manufacturing method of this CSP will be described below. In
FIG. 32
, a flowchart entitled as a glass epoxy/flexible substrate in the center is referred to.
First of all, a glass epoxy substrate
5
as the base substance (support substrate) is prepared. The Cu foils
20
,
21
are bonded via an insulating adhesive on the both sides (see FIG.
31
A).
Subsequently, Cu foil
20
,
21
corresponding to the first electrode
7
, the second electrode
8
, the die pad
9
, the first back electrode
10
, the second back electrode
11
, are covered with an anti-etching resist
22
, and then the Cu foils
20
,
21
are patterned. The patterning may be performed separately on the front and back sides (see FIG.
31
B).
Subsequently, a pore for the through hole TH is formed through the glass epoxy substrate, using a drill or laser. Then, this pore is plated to make the through hole TH. Via this through hole TH, the first electrode
7
and the first back electrode
10
, as well as the second electrode
8
and the second back electrode
11
are electrically connected (see FIG.
31
C).
Further, though omitted in the drawings, the first electrode
7
and the second electrode
8
which become the bonding posts are plated with Au, and the die pad
9
which becomes a die bonding post is plated with Au to make die bonding of the transistor chip T.
Lastly, the emitter electrode of the transistor chip T and the first electrode
7
, as well as the base electrode of the transistor chip T and the second electrode
8
are connected via the bonding wire
12
, and covered with the resin layer
13
(see FIG.
31
D).
As required, the individual electrical elements are divided by dicing. In
FIG. 31
, the glass epoxy substrate
5
is only provided with one transistor chip T, but practically, a number of transistor chips T may be provided like a matrix. Therefore, the electrical elements are separated individually by a dicing apparatus lastly.
With the above manufacturing method, the CSP type electrical element employing the support substrate
5
can be completed. This manufacturing method is also applicable to the case of employing a flexible sheet as the support substrate.
On the other hand, a manufacturing method employing a ceramic substrate is shown in a flowchart to the left of FIG.
32
. After the ceramic substrate to make the support substrate is prepared, a through hole is formed. Then the front and back electrodes are printed using a conductive paste, and sintered. Thereafter, the steps are performed in the same way as the manufacturing method of
FIG. 31
up to covering the resin layer in the previous manufacturing method. However, the ceramic substrate has the problem that it is very fragile, and easily breaks off, unlike the flexible sheet or glass epoxy substrate, and can not be molded using a mold. Therefore, the sealing resin is potted, cured, and then polished to make a flat surface. Lastly, the electrical elements are separated using a dicing apparatus.
Further there is a demand for a lithium ion cell of small size and large capacity with the spread of portable terminals. A protection circuit substrate for battery management of charging or discharging this lithium ion cell must be small in size and withstand the short-circuit with the load, owing to the needs for the lighter portable terminal. Such protection circuit substrate is accommodated within a container of the lithium ion cell, and required to be smaller and thinner. For this purpose, the COB (Chip on Board) technology making use of a lot of chip components was freely employed to meet the demands for the smaller and thinner constitution. On the other hand, since a switching element is connected in series with the lithium ion cell, the on resistance of this switching element needs to be suppressed to a quite small value, which is an essential factor to lengthen the service time or stand-by time in the portable telephone.
In order to implement this small on resistance (RDS (on)), the chips with increased cell density were developed by using minute processing in manufacturing the chips.
More specifically, a planar structure in which the channels are formed on the surface of semiconductor substrate had a cell density of 7,400,000 cells/square inches, and an on resistance of 27 m&OHgr;. However, in the first generation of trench structure in which channels are formed on the side face of trench, the cell density was greatly increased to 25,000,000 cells/square inches, and the on resistance was decreased to 17 m&OHgr;. Further, in the second generation of trench structure, the cell density was 72,000,000 cells/square inches, and the on resistance was decreased to 12 m&OHgr;. However, there are some limitations on the minute structure to further decrease the on resistance.
FIG. 34
is a cross-sectional view of a power MOSFET that is mounted on the protection circuit substrate. There is a
Etou Hiroki
Fukuda Hirokazu
Kobayashi Yoshiyuki
Maehara Eiju
Mashimo Shigeaki
Fish & Richardson PC
Ho Tu-Tu
Nelms David
Sanyo Electric Co,. Ltd.
LandOfFree
Circuit device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3010853