Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-10
2002-07-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06418553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a circuit designing method for a semiconductor device, and a computer-readable medium. More specifically, the invention relates to a circuit designing method for a semiconductor device, which uses a half-tone phase shift mask for forming a circuit pattern on a semiconductor substrate, and a computer-readable medium having recorded a program for causing a computer to execute the circuit designing method.
2. Description of the Prior Art
In recent years, the scale down of a semiconductor device has been accelerated. For that reason, the development of a material, system and method for easily processing a fine pattern on a semiconductor substrate does not follow the speed of the scale down, so that it is difficult to ensure a process tolerance required for the production of the device. In the field of lithography, various super resolution exposure methods have been proposed as techniques for improving the process tolerance using a conventional system. For example, a half-tone phase shift mask is widely used since it is relatively easy to prepare a mask. However, if the half-tone phase shift mask is used, there are some cases where a secondary light peak called a side lobe is produced at a place other than a desired pattern. When the side lobe is transferred to a positive or negative resist, the resist has a defect so that the thickness of the positive resist decreases or the negative resist remains. As a result, there is a problem in that the effective process tolerance decreases. In order to avoid this problem, the light intensity of the side lobe has only to decrease. For example, there have been used a method for increasing a coherence factor &sgr; which is one of illumination conditions of an aligner, a method for providing a master pattern with a bias quantity to increase the size of an opening, a method for decreasing a half-tone phase transmittance, and so forth.
However, these techniques decrease the process tolerance of a desired pattern itself although the techniques avoid the transfer of the side lobe. Therefore, it is required to optimize the conditions for avoiding the transfer of the side lobe and for ensuring the process tolerance of a desired pattern. However, since the light intensity of the side lobe greatly depends on a pattern layout, there is also a problem in that even if the optimized conditions for preventing the influence of the side lobe in a certain pattern layout are used, the influence of the side lobe is strong in another pattern layout. Thus, it is strongly desired to reduce the influence of the side lobe in all of pattern layouts and to ensure a required and sufficient process tolerance. On the other hand, it is required to provide an optical simulator capable of taking account of the process tolerance including the influence of the side lobe, as a tool for efficiently optimizing illumination conditions and a master bias. In a conventional optical simulator, as one of techniques for taking account of the influence of the side lobe, there is a method for slicing an image by the light intensity, by which a desired pattern having a desired dimension is finished in the best focus, to monitor an image contour line produced in a place other than the desired pattern. However, this technique is not applicable since it is qualitative and can not take account of the difference at the level of the transfer of the side lobe which varies in accordance with the resist process. Similarly, there is a method for deriving a ratio of an edge light intensity when a desired pattern having a desired dimension is finished in the best focus, to a side lobe light intensity as a threshold. In this technique, when the threshold is
1
in the case of only an optical image, the influence of the resist process is expressed by a decimal as a proportion thereof, so that it is possible to quantitatively evaluate the difference in resist process. However, when the light exposure varies or when defocusing occurs, the threshold has a different value, so that this technique is not applicable in the evaluation of the process tolerance, which must take account of both of the influence of the light exposure and the influence of the defocusing. Moreover, a technique for varying the pattern layout to calculate the side lobe light intensity to extract a pattern layout rule which is easily influenced by the side lobe is proposed in, e.g., “H. Kim et al., Pros. SPIE, Vol. 3334, Optical Microlithography, p532 (1988)”. However, in this proposal, it is not clear how much the side lobe light intensity is decreased to obtain a sufficient process tolerance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a circuit designing method for a semiconductor device, which can remove the influence of a produced side lobe pattern and ensure a required and sufficient process tolerance when a half-tone phase shift mask is used, and a computer-readable medium having recorded a program for causing a computer to execute the circuit designing method.
In order to accomplish the aforementioned and other objects, the inventors prepared a design rule using only a region capable of obtaining a required and sufficient process tolerance by calculating a side lobe transfer characteristic value for a resist process and by quantifying a process tolerance in each of pattern layouts using the transfer characteristic value.
According to the first aspect of the present invention, there is provided;
a circuit designing method for a semiconductor device, which uses a half-tone phase shift mask for forming a circuit pattern on a semiconductor substrate, the method comprising: a first step of extracting a basic pattern representative of the circuit pattern from design information; a second step of setting parameters serving as conditions for a circuit design; a third step of calculating a first lithography process tolerance, which is an index satisfying a range of a dimensional fluctuation allowed when the basic pattern is formed on the semiconductor substrate, using an optical simulation; a fourth step of a second lithography process tolerance, which is an index capable of avoiding the formation of a side lobe capable of being produced on the semiconductor substrate when the basic pattern is formed on the semiconductor substrate using the half-tone phase shift mask, using an optical simulation; a fifth step of calculating a common lithography process tolerance comprising an overlapping region of the first lithography process tolerance and the second lithography process tolerance; a sixth step of preparing an inhibiting rule for excluding a circuit pattern including the basic pattern, which is below a reference value previously set on the basis of the common lithography process tolerance, from an object to be designed; and, a seventh step of designing a circuit using the inhibiting rule.
According to the second aspect of the present invention, there is provided;
a computer-readable medium for use in a circuit designing system for designing a semiconductor device using a half-tone phase shift mask for forming a circuit pattern on a semiconductor substrate, the medium having recorded a program for causing a computer to execute a circuit designing method for the semiconductor device, the method including: a first procedure for extracting a basic pattern representative of the circuit pattern from design information; a second procedure for setting parameters serving as conditions for a circuit design; a third procedure for calculating a first lithography process tolerance, which is an index satisfying a range of a dimensional fluctuation allowed when the basic pattern is formed on the semiconductor substrate, using an optical simulation; a fourth procedure for a second lithography process tolerance, which is an index capable of avoiding the formation of a side lobe capable of being produced on the semiconductor substrate when the basic pattern is formed on th
Hashimoto Koji
Mimotogi Shoji
Yamada Akiko
LandOfFree
Circuit designing method for semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit designing method for semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit designing method for semiconductor device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2897680