Circuit design method and computer program product

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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06928631

ABSTRACT:
A circuit design technology which can facilitate timing adjustment for a circuit whose layout has been designed. The circuit design method including the steps of entering design data for a circuit including a variable delay cell inserted in advance at a part where delay adjustment is expected necessary in terms of a circuit characteristic during an initial layout, analyzing timing of the entered design data, and correcting the delay in the variable delay cell when an error occurs as a result of the timing analysis.

REFERENCES:
patent: 6272668 (2001-08-01), Teene
patent: 6425115 (2002-07-01), Risler et al.
Patent Abstracts of Japan of JP 4-288717 A dated Oct. 13, 1992.
Patent Abstracts of Japan of JP 4-333261 A dated Nov. 20, 1992.

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