Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-31
2001-05-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06226780
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of circuit design. More particularly, this invention relates to the art of circuit design supporting a plurality of hardware design languages.
2. Background
Integrated circuit design is often undertaken using one or the other of the two industry standard hardware design languages (HDL). Very high speed integrated circuit (VHSIC) hardware design language (VHDL) and Verilog are both IEEE standard HDLs and each has about equal market share with some geographical variances. VHDL and Verilog can be used to describe the structure and function of an integrated circuit design at numerous levels of abstraction. Both HDLs can be compiled into machine readable form allowing designs to be simulated and verified before being manufactured. Using VHDL and Verilog, designers can quickly compare alternative designs and test design criteria without the delay and expense of hardware prototyping.
Designing an integrated circuit using only an HDL can be incredibly difficult and time consuming because an HDL file is purely textual. Many designers feel more comfortable using graphical design tools. Graphical design tools often support either VHDL or Verilog, based on the assumption that a single HDL will be used throughout the downstream design flow. In which case, when HDL files are automatically generated to describe a graphical circuit design, the HDL files are usually provided in only one HDL format, either VHDL or Verilog. To provide the circuit design in both VHDL and Verilog, it may be necessary to use two graphical entry tools. Since graphical entry tools can be very expensive, design houses have historically invested in either a Verilog design flow or a VHDL design flow, but not both.
Supporting a single HDL may not pose a problem when a circuit design goes from conception to production within a single design house. As design complexity continues to increase however, new designs are frequently based on existing designs or legacy design data. A market has developed for legacy data, often called intellectual property (IP) blocks or “system-on-silicon” building blocks. For instance, existing microprocessor blocks or digital signal processor (DSP) cores, written in an HDL, may be purchased from an outside source and imported into a new design, potentially reducing the time to market for the new technology.
Unfortunately, an IP block may only be available in one HDL since design houses frequently only support one HDL. In which case, the advantage of using an IP block is virtually eliminated if the HDL in question is not supported. The problem is compounded as global circuit design becomes more common. For instance, even within a single business entity, a library of IP blocks may be generated in VHDL at one location where VHDL is prevalent. Then, the library may be provided in another location where Verilog is prevalent. Obviously, the utility and marketability of IP is limited by HDL compatibility between producer and consumer.
Thus, a need exists for an integrated circuit design method and apparatus that can support multiple HDLs in both the creation of new circuit designs and the use of legacy data such as IP blocks.
SUMMARY OF THE INVENTION
The present invention beneficially provides a method and apparatus that can support multiple HDLs in both the creation of new circuit designs and the use of legacy data such as IP blocks. Where a graphical design tool supports a first HDL and design data is provided in a second HDL, the present invention generates an interface description for the design data written in the first HDL, and then generates a graphical design unit based on the interface description. The resulting graphical design unit is supported by the graphical design tool.
REFERENCES:
Martinolle et al., “A Procedural Language Interface for VHDL and its Typical Applications,” Proc of NC/VIUF, pp. 32-38, 1998.*
Mathur et al., “HDL Generation From Parameterized Schematic Design System,” IEEE, pp. 130-134, 1997.*
Sauge et al., “Integrating of Verilog-HDL and VHDL Languages in the SMASH™ Mixed-Signal Multilevel Simulator,” Proc. IVC/VIUF, pp. 2-6, 1998.*
Ussery et al., “HDL and Integrating System-Level Simulation Technologies”, IEEE, pp. 91-97, 1997.*
Verschueren, “Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard HDLs”, Proc. 24thEuromicro Conf., pp. 42-45, 1998.
Bahra Avtar Singh
Dane Mark
Reynolds Mike J.
Walker Gordon
Columbia IP Law Group, LLC
Garbowski Leigh Marie
Mentor Graphics Corporation
Smith Matthew
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