Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2002-03-22
2003-06-03
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185010, C365S189011
Reexamination Certificate
active
06574152
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories and in particular a a circuit for multiple input voltages for use with EEPROM flash memory.
2. Description of the Related Art
High voltage charge pump circuits and area consuming state machines are built into flash EEPROM memory chips for systems requiring programmability. The use of these chips in systems that do not require programmability are a waste of space and result in increased die cost and noise. For EPROM memories there are no requirements for high voltage charge pump circuits and on chip state machines. Any data changes for EPROM memory relies on electrical program and ultra-violet (UV) light erase operations. The UV erase changes the threshold voltage Vt to a low state and requires a costly package with a quartz window to allow the UV light to reach the surface of the chip die.
After a predetermined UV erase time of around 15 minutes, the electrons will be ejected out of the floating gate of all EPROM cells. This results in the Vt of all cells to be lowered to approximately ±1.2V resulting in a logical “1”. The UV erase operation is similar to chip erase in a flash EEPROM. After UV erase, any selected data change from “1” to “0” requires an electric program operation. The program operation is done by either a high current channel hot electron (CHE), or by low current Fowler Nordheim (FN) schemes. For a CHE program, a positive high voltage ranging from +10V to +12V is required. By contrast, FN program operation requires a negative high voltage ranging from −10V to −12V. For today's low voltage single power supply memory, a positive high voltage is generated from an on chip charge pump. High voltage supply pins, like VPP as required in traditional EPROM memory, are removed from the standard pin configuration of a flash EEPROM. The negative high voltage supply VNN is not needed for the traditional EPROM memory and is created on chip for the flash EEPROM. The VNN can be used either for FN program or erase operations. The penalty for on chip positive and negative charge pumps is an increase in die area and cost. In addition, on chip charge pumps generate substantial noise, which degrades the system performance and causes operation failures at low chip bias voltage Vdd.
U.S. Pat. No. 5,848,000 (Lee et al.) is directed toward the use of a plurality of voltage terminals to receive a plurality of voltages to facilitate accurate and flexible read, erase and program operations for a flash memory. U.S. Pat. No. 5,748,538 (Lee et al.) is directed toward providing a flash electrically erasable programmable read only memory (EEPROM), where writing, e.g. erasing and programming, of a selected cell uses an FN tunneling method.
For those applications requiring no in system programmability and having a strong demand for low die cost and low noise, the on chip charge pumps and state machine must be removed. Therefore, off chip positive (VPP) and negative (VNN) high voltage power supplies are required. Also, adding VNN to any existing selective pins of an EPROM, a pin compatibility for JEDEC standard has to be maintained.
SUMMARY OF THE INVENTION
An object of the present invention is to remove the on chip high voltage negative and positive charge pumps thereby eliminating the noise and achieving stability of a low Vdd operation and with the negative high voltage VNN being supplied from an external pin for the erase operation;
Another object of the present invention is to remove the on chip state machine to reduce the die area and required circuit design for cost reduction;
A further objective of the present invention is to add VNN to the preferred pin set of the traditional EPROM, and thereby meeting full compatibility in the read operation for those applications requiring no in system programmability;
Still a further objective of the present invention is to add VNN to the preferred pin set of a standard EPROM and maintain the JEDEC standard;
Still another further objective of the invention is to provide a novel input circuit solution that can accept three voltages for different operations of flash EEPROM in MTP (multiple time programmable memories) application using the same package pin and without a costly package using a quartz window.
The present invention teaches a novel input circuit design that can accept more than three supplied voltages for different operations of EEPROM flash memory using the same package pin. These voltages include a first voltage of positive power supply VDD, or any positive voltage; a second voltage of ground level, or Vss; and a third voltage of a negative power supply VNN, or any negative voltage. The voltages VDD, VSS and VNN are supplied to the same input pad for different flash operations at different times. For example, in one embodiment, the VNN, VDD and VSS are supplied to the CEB pin of an EPROM memory. In this EPROM memory, CEB pin is traditionally used as a chip enable pin.
When VDD is connected to the CEB pin, the EPROM chip is disabled and is set into the standby mode. In this condition, the chip will not consume any power and all input and output buffers are disabled. The output buffers are in tri-stated (high impedance) state. When ground is connected to the CEB pin, the chip is enabled. The output buffers are released from tri-state mode and output their stored data. Unlike a UV-EPROM, an electric erase operation is needed for data change for the flash memory. In accordance with the present invention, the electric erase operation requires a negative high voltage which is supplied to the CEB pin. This negative high voltage is approximately around −10V, or less, to allow flash cells to perform an FN erase operation, which is also required in other flash operation such as erase verify.
The operating principles of the three voltage input circuit of the present invention is described in reference to FIG.
1
through FIG.
6
. The three different voltages include a first voltage of positive power supply VDD, or any positive voltage; a second voltage of ground level of VSS; and a third voltage of negative power supply VNN, or any negative voltage. According to the present invention, VDD, VSS and VNN are all supplied to the same chip input pad for different flash operations at different times. In order to be consistent with traditional EPROM devices, the selection of the pad for the three voltage input circuit can be used for CEB (chip enable bar), OEB (output enable bar), PGMB (program bar), or other functions depending on the density of the memory.
The design targets of the present invention are: 1) To select a traditional EPROM's pin that can be added to the erase function and make the pin a multiple-function pin. The preferred pin selection is varied for different density of EPROM memory. 2) To allow the selected pin to accept more than three voltages such as VDD, VSS and VNN, or other voltages between VDD and VNN. Where VDD is the positive power supply, VSS is the ground voltage, and VNN is the external negative power supply of around −10V for performing a write operation. The write operation requires the external negative supply of VNN for either program or erase operations according to the present invention. 3) To allow the selected multi-function pin to provide proper external voltages for either read or write operations. For example, when the read function depends on the selected pin, CEB is selected to couple VNN to the chip. Then during the read operation the multi-function pin functions as CEB (Chip-Enable-Bar) to control enable or disable of the chip. During an erase operation the multi-function pin is used to connect a high negative voltage, such as VNN, to the chip. 4) to allow the requirement of device breakdown to be kept below IVNNI+VDD, where IVNNI is defined as the absolute value of the VNN voltage. With VNN=−10V and VDD=+3V, the breakdown voltage of IVNNI+VDD is 13V. 5) to allow the multi-function pin VNN/GEB to consume zero standby c
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Lam David
Saile George O.
LandOfFree
Circuit design for accepting multiple input voltages for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit design for accepting multiple input voltages for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit design for accepting multiple input voltages for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3144372