Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-26
2003-04-01
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06543033
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-87664, filed on Mar. 27, 2000, the entire contents of which are incorporated herein by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit design apparatus, a circuit design method, and a circuit design program for automatically generating arrangement/wiring information of logical blocks in a circuit by using design information about the circuit, and a semiconductor for integrated circuit fabrication method of fabricating a semiconductor integrated circuit based on the arrangement/wiring information, and, more particularly, to a technique to increase the efficiency of the circuit design and of the semiconductor int grated circuit fabrication process significantly.
2. Description of the Related Art
At present, there are various methods and configuration techniques to increase the operation speed of a semiconductor integrated circuit. How ver, the performance of the semiconductor integrated circuit is often extremely decreased or the circuit characteristic is to be required cannot be often achieved under the relationship of delays among input signals supplied to logical blocks in the circuit to be design. In order to avoid those cases, the designer must handle a part of the design process of the circuit by manual.
For example, in order to drive the circuit under optimum state, the designer must set various kinds of conditions. For example, following conditions must be necessary:
An evaluation of a logical block must be initiated after the level of a clock signal clock signal ck is switched and the transmission of an input signal from a preceding logical block to a node in a following logical block is also completed simultaneously; and
The evaluation of the following logical block must be completed adequately before a pre-charging for the preceding block in a preceding stage by a following clock signal is initiated.
However, in the conventional timing design process for such the case, the designer must adjust the circuit parameters only by manual in order to drive the circuit in the optimum state.
Accordingly, it is extremely difficult for the designer to design the optimum arrangement in the target circuit having the highest performance, because such the conventional circuit design method requires consideration of both the logical delay and the wiring delay estimated from the arrangement of logical blocks in a final circuit layout. Further, the conventional circuit design method by manual requires a long design time period. This causes to decrease the efficiency of the circuit design process.
In order to avoid this conventional drawback of the circuit design described above, it s possible to use a CAD (Computer Aided Design) technique. However, although the conventional CAD technique can design a circuit so that a clock signal is transferred to each logical block simultaneously, it cannot delay the clock signal in consideration of the relationship between the input signal supplied to the logical block and the clock signal. Accordingly, it is difficult to perform a circuit design with high accuracy.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a circuit design apparatus, a circuit design method, a circuit design program, and semiconductor integrated circuit fabrication method capable of extremely increasing the efficiency of a circuit design process with high accuracy.
The inventors have deduced a new idea from the consideration of the delay of input signals to be supplied into logical blocks in a target circuit to be design. That is, the inventors have obtained the resent invention to increase the efficiency of the circuit sign process when the automatic arrangement/wiring process s performed so that the difference of delay times among the input signals to be input to the logical blocks is set in limitation conditions and a clock signal to be supplied to the logical blocks is delayed. The inventors have invented the technical idea including the following features based on the result of a continuous aggressive study.
In accordance with a preferred embodiment of the present invention, a circuit design apparatus determines an arrangement and wiring of logical blocks n a circuit by using circuit design information. The circuit design apparatus comprises an arrangement/wiring section or determining an arrangement and wiring of the logical blocks in the circuit so that both delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are satisfied.
In accordance with another preferred embodiment of the present invention, a circuit design method determines an arrangement and wiring of logical blocks in a circuit by using circuit design information. The circuit design method includes the steps of: inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals; and determining the arrangement and the wiring of the logical block in the circuit so that both the delay limitation information and the limitation conditions are satisfied.
In accordance with another preferred embodiment of the present invention, a circuit design program to be used for executing a circuit design method of determining an arrangement and wiring of logical blocks in a circuit by using circuit design information. The circuit design program includes the programs of: inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals; and determining the arrangement and the wiring of the logical blocks in the circuit so that both the delay limitation information and the limitation conditions are satisfied.
According to the circuit design apparatus, the circuit design method and the circuit design program of the present invention, it is possible to perform the circuit design process automatically to design circuits of higher speed operation, a part of which is designed by manual in the prior technique, by the automatic arrangement/wiring process. In addition, it is also possible to extremely improve the efficiency of the circuit design process.
In accordance with another preferred embodiment of the present invention, a semiconductor integrated circuit fabrication method fabricates a semiconductor integrated circuit. This fabrication method comprises the steps of: the step of inputting circuit design information that are obtained by determining an arrangement and wiring of logical blocks so that the following delay limitation information and limitation conditions are satisfied; and the step of fabricating the semiconductor integrated circuit by performing the arrangement and wiring of the logical blocks based on the circuit design information. In this case, the delay limitation information is the information about input signals to be supplied to the logical blocks, and the limitation conditions are the conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals.
Thereby, it is possible to perform the circuit design process efficiently and also to reduce the fabrication process period of the semiconductor integrated circuit.
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patent: 5787268 (1998-07-01), Sugiyama et al.
patent: 5892685 (1999-04-01), Sugiyama et al.
patent: 6009248 (1999-12-01), Sato et al.
patent: 6090150 (2000-07-01), Tawada
patent: 6148432 (2000-11-01), Brown
pa
Ikumi Nobuyuki
Yamazaki Itaru
Kabushiki Kaisha Toshiba
Lam Tuan T.
Nguyen Hai L.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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