Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-11-15
2001-10-02
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S145000, C365S200000
Reexamination Certificate
active
06297995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component.
Before being delivered to customers, semiconductor components, such as semiconductor memories, are tested as to whether they still operate properly at specific temperatures. This was previously done by placing a semiconductor memory in a tester in which the temperature applied to the semiconductor memory can be set externally. As soon as this temperature, for example 87° C. is attained, the semiconductor memory in the tester is tested for its functionality through the application of specific test signals applied to it.
If the temperature in the tester cannot be regulated, the test results are often unsatisfactory because certain characteristics of a semiconductor memory are strongly dependent on the temperature. The possibility therefore definitely exists that at the test temperature, for example above 87° C., it is not possible to detect reliably every possible defect in the semiconductor memory.
From the IEEE article “TRANSACTION ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS”, Vol. 5, No. 3, September 1997, pp 270-276, CMOS sensors are known which consist of MOS circuits and which can be installed in integrated circuits for recording temperature. This publication does not, however, deal with the testing of memories.
Finally, Published, Non-Prosecuted German Patent Application DE 198 28 192 A1 discloses a circuit configuration for controlling the chip temperature of a semiconductor memory to be measured, in which circuit configuration at least one temperature sensor is provided in the chip having the semiconductor memory. In the chip, the semiconductor memory and the temperature sensor are connected with a temperature control unit. This enables a chip temperature of the semiconductor memory to be set to different values so that good test coverage can be achieved even if particular characteristics of the semiconductor memory are strongly dependent on temperature.
However, this prior art circuit configuration does not make possible the immediate repair of the semiconductor memory in the process of being tested. On the contrary, a repair of the semiconductor memory cannot be performed until the test has been completed, which repair can be carried out, for example, using normal laser fuses which are blown in the semiconductor memory according to the defective sites located during the test.
Another possibility consists therein, that a semiconductor memory is tested and repaired at every start-up of the semiconductor memory by a test and repair logic circuit provided on the chip. In other words, the repair is carried out directly on the chip having the semiconductor memory. A procedure of this kind can, however, deliver unsatisfactory results because in this case the semiconductor memory is not tested at the respective operating temperature required.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a semiconductor component of the configuration can be repaired easily after being tested at different temperatures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, which contains a semiconductor chip, including: a semiconductor component; a self-test and repair logic circuit connected to the semiconductor component; and at least one temperature sensor connected to the self-test and repair logic circuit, the at least one temperature sensor measuring a temperature of the semiconductor chip.
This object is achieved according to the invention in a circuit configuration of the kind named at the beginning, in that the semiconductor component, the temperature sensor and the self-test and repair logic circuit are connected to each other in the semiconductor chip.
Thus in addition to the semiconductor component and the temperature sensor, the circuit configuration also contains the self-test and repair logic circuit within the semiconductor chip so that not only can the temperature be set for the test procedure—as in the circuit configuration according to the Published, Non-Prosecuted German Patent Application DE 198 28 192 A1 but also a repair can be simply carried out after the test procedure at every start-up or at other suitable times. The repair, i.e. the replacement, for example, of defective memory sites in a semiconductor memory as the semiconductor component, can be carried out either permanently and statically by blowing appropriate laser fuses, or temporarily by connecting redundant memory elements in separate registers.
In this way the invention makes possible an advantageous combination of a repair using a self-test and repair logic circuit, with a temperature-dependent test using a temperature sensor contained in the semiconductor chip having the semiconductor component.
In a concrete example the circuit configuration according to the invention contains a semiconductor memory as the semiconductor component. The semiconductor chip having the semiconductor memory additionally includes the temperature sensor, for example a temperature-dependent oscillator, and the self-test and repair logic circuit (BIST). If a “self-repair” of the semiconductor memory should now be performed by the circuit configuration, its temperature is first checked using the temperature sensor. If the measured temperature is not suitable for the test, the BIST switches on a temperature-modification mode. The self-test begins as soon as the temperature sensor reports that the appropriate temperature has been reached. If during the test the temperature again deviates from the appropriate temperature, the self-test is aborted and the temperature-modification mode is switched on briefly once again. In this way it can be ensured that the semiconductor memory is tested at the appropriate temperature.
After all defective memory cells have been located, an appropriate repair configuration is worked out in the BIST in order then to perform the repair, for example by setting a register for redundant memory cells or through programming electrically settable fuse blocks. As soon as the repair of the semiconductor memory is complete it is reported as free of errors. If such a repair is not possible, this can also be displayed as information.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5406212 (1995-04-01), Hashinaga et al.
patent: 6157585 (2000-12-01), Kim
patent: 715 176 A2 (1996-06-01), None
“CMOS Sensors for On-Line Thermal Monitoring of VLSI Circuits”, Vladimir Szekely et al., IEEE transactions on very large scale integration (VLSI) systems, vol. 5, No. 3, Sep. 1997.
Mc Connell Roderick
Richter Detlev
Fears Terrell W.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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