Circuit configuration with a microprocessor

Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration

Reexamination Certificate

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Details

C710S262000, C714S023000

Reexamination Certificate

active

06173396

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit arrangement having a microprocessor, whose reset terminal is adapted to receive a reset signal from a driving circuit.
BACKGROUND IMFORMATION
In conventional circuit arrangements which include a microprocessor, the driving circuit of the reset terminal of the microprocessor is implemented by a voltage regulator designed to emit the reset signal.
German Patent No. 43 02 232 describes a circuit arrangement which includes a microprocessor. A wake-up signal is periodically provided to bring a microprocessor, which is in an inactive state, into an active operating state. However, no further explanations regarding a driving circuit for a reset terminal are described in this publication.
SUMMARY OF THE INVENTION
An object of the present invention is to provided a circuit arrangement which will render possible a simple driving circuit.
In accordance with the present invention, the reset terminal is coupled to a further terminal of the microprocessor, which, after the reset terminal has received the reset signal, holds the reset terminal at a defined suppressing level that deviates from the reset level.
The present invention provides an arrangement in which an initial reset pulse effects the reset operation when the microprocessor is put into operation. After that, reset pulses are suppressed at the reset terminal. In this manner, a simple signal can be used that is present when the microprocessor is put into operation, at the reset instant, the signal assuming a level corresponding to the reset level, and after that being able to deviate from the reset level, without the need for costly wiring or a costly voltage regulator.
In one exemplary embodiment of the present invention, the additional terminal is held at the suppressing level by programming the microprocessor. After the microprocessor has left the reset state, following the change in the reset signal from the reset level, as one of the first commands to be executed, it sets the additional terminal, which is connected in parallel to the reset terminal, to the suppressing level, and holds it at this level during the processor's operating state, so that further reset signals are not able to appear at the reset terminal.
Provision can be made, for example, for the reset level to be the L-level (low level), and for the suppressing level to be the H-level (high level), and for the suppressing level to be maintained during the microprocessor's active state by internal protective structures of the microprocessor and by an external circuit element. In this manner, the suppressing level is maintained in a defined manner. Internal protective structures of this kind may be provide in which, for example, the additional terminal is connected to ground via a diode linked in blocking direction, and is connected to supply-voltage potential via another diode linked in the forward-conducting direction. The external circuit elements may include a simple resistor in a supply line of the reset signal.
One simple way to make the reset signal available is for the reset signal to be tapped off from a setpoint signal supplied by a control circuit, the setpoint signal also being used in a voltage-supply stage for reducing the closed-circuit quiescent current. Thus, the setpoint signal, i.e. the control circuit supplying it, is doubly utilized.


REFERENCES:
patent: 4429366 (1984-01-01), Kennon
patent: 4520418 (1985-05-01), Susi
patent: 4638428 (1987-01-01), Gemma et al.
patent: 4788661 (1988-11-01), Morita
patent: 4807141 (1989-02-01), Keine
patent: 4860289 (1989-08-01), Coulson
patent: 5054448 (1991-10-01), Matsuoka et al.
patent: 5157270 (1992-10-01), Sakai
patent: 5313112 (1994-05-01), Macks
patent: 5345583 (1994-09-01), Davis
patent: 5522040 (1996-05-01), Hofsass et al.
patent: 5704034 (1997-12-01), Circello
patent: 43 02 232 (1994-08-01), None
patent: 60-081651 (1985-05-01), None
patent: 8-10867 (1996-04-01), None

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