Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2006-10-24
2006-10-24
Nguyen, Vincent Q. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C323S316000
Reexamination Certificate
active
07126354
ABSTRACT:
A circuit configuration has a load transistor and a current measuring configuration. A method ascertains a load current through a load transistor. The circuit configuration includes a first and a second current sensor with a current measuring transistor in each case. Each of the current sensors provide a current measurement signal that is fed to an evaluation circuit. The evaluation circuit provides, from the first current measurement signal, a current measurement signal that is dependent on the load current. The load transistor and the current measuring transistors are preferably integrated in a common semiconductor body having a multiplicity of transistor cells of identical construction. The evaluation circuit preferably accounts for the spatial position of the cells of the first and second current measuring transistors in the cell array.
REFERENCES:
patent: 5099186 (1992-03-01), Rippel et al.
patent: 5144514 (1992-09-01), Sekigawa
patent: 5375029 (1994-12-01), Fukunaga et al.
patent: 5568343 (1996-10-01), Kosugi
patent: 5663574 (1997-09-01), Hierold et al.
patent: 5815027 (1998-09-01), Tihanyi et al.
patent: 5867014 (1999-02-01), Wrathall et al.
patent: 6011413 (2000-01-01), Hayakawa et al.
patent: 6538289 (2003-03-01), Topp et al.
patent: 6737856 (2004-05-01), Sander
patent: 6788088 (2004-09-01), Throngnumchai
patent: 7009403 (2006-03-01), Graf et al.
patent: 2002/0101225 (2002-08-01), Oyrer
patent: 40 20 187 (1991-01-01), None
patent: 43 34 386 (1994-04-01), None
patent: 44 34 894 (1996-04-01), None
patent: 195 20 735 (1996-12-01), None
patent: 198 25 029 (1998-12-01), None
patent: 198 23 768 (1999-12-01), None
patent: 198 44 665 (2000-03-01), None
patent: 199 58 234 (2001-06-01), None
patent: 101 03 920 (2002-08-01), None
patent: 0 397 102 (1990-11-01), None
patent: 0 688 077 (1995-12-01), None
Jens Peer Stengl et al.: :Leistungs-MOS-FET-Praxis” [power MOS FET practice],Pflaum Verlag Müchen, 2nded., 1992, pp. 32-32-35.
Deboy Gerald
Zverev Ilia
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Hoai-An D.
Nguyen Vincent Q.
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