Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-03-13
2003-10-28
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S149000, C327S150000, C327S151000
Reexamination Certificate
active
06639958
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention pertains to delay locked loops and, more particularly, to a circuit configuration for the interference-free initialization of delay locked loop circuits (DLL circuits) with fast lock, in which
an on-chip clock signal is synchronized with an external clock signal by means of a delay line driven via a phase detector, a filter, a counter device and a digital/analog converter; and
the counter device comprises at least one higher-order counter and a lower-order counter, which can each be triggered by a counter clock signal and can alternatively be activated and deactivated by means of a control signal, in order to shorten the time taken to adjust the DLL.
In integrated circuits having, for example, a so-called Rambus interface, a clock signal fed in externally to the integrated circuit is required at numerous locations. This presupposes a high gain for the clock signal fed in externally. However, such a high gain is inevitably associated with corresponding delay times. Therefore, an internal clock signal is preferably generated from an external clock signal and is fed with a time shift, with the correct phase angle in each case, to those locations of the integrated circuit which require such a clock signal.
The conversion of an external clock signal into an internal clock signal having the desired phase angle is, therefore, a problem which arises generally in integrated circuits.
The block circuit of
FIG. 4
diagrams the structure of a circuit configuration used to obtain an internal clock signal Ti from an external clock signal Te. For this purpose, the external clock signal Te is fed to a voltage-controlled delay line
1
, which supplies the internal clock signal Ti synchronized with the external clock signal Te. For this purpose, the voltage-controlled delay line
1
can be driven by a control signal in such a way that its delay is variable. This control signal is expediently generated by a phase detector
2
and a filter
3
. By means of the phase detector
2
, firstly the phase of the internal clock signal Ti at the output of the voltage-controlled delay line
1
is compared with the phase of the external clock signal Te at the input of the delay line. A signal representing the comparison result is fed to the filter
3
, which expediently comprises a low-pass filter component, in order to bring the delay time of the voltage-controlled delay line
1
slowly to the desired length.
A circuit configuration corresponding to
FIG. 4
is described in detail for example by Sidiropoulos and Horowitz, in “A Semidigital Dual Delay-Locked-Loop,” IEEE Journal of Solid-State Circuits, Volume 32, No. 11, Nov. 1997, Pages 1683-92.
FIG. 5
shows a circuit configuration which is derived from the circuit configuration disclosed in the afore-mentioned document. In detail,
FIG. 5
illustrates a DLL circuit in which the output of the phase detector
2
, which is located between the input and the output of the voltage-controlled delay line
1
, is connected to the control input of the voltage-controlled delay line
1
via a digital low-pass filter
4
, a digital counter
5
and a digital/analog converter
6
. The digital counter
5
counts up or down depending on the level of the output signal of the digital low-pass filter
4
. A clock signal clk_count for the digital counter
5
is generated from the high-frequency external clock signal Te by the clock signal Te being divided down by means of a frequency divider
7
, as a result of which a low-pass filter behavior is achieved for the digital counter
5
.
The current counter reading of the digital counter
5
is converted, with the aid of the digital/analog converter
6
, into an analog control signal delay_control, which finally influences the length of the voltage-controlled delay line
1
.
In order, in the case of this circuit configuration, to shorten the time taken to adjust the DLL during initialization, a control signal “fast” is introduced, which triggers the digital counter
5
during initialization. In addition, the initialization is subdivided into two phases: the signal “fast” is activated in a first phase, while it is deactivated in the second phase. During the first phase, in which the control signal “fast” is activated, the lower-order bits of the digital counter
5
are deactivated and the higher-order bits are directly addressed.
For this purpose, the digital counter
5
is subdivided into two units, namely, as is shown in
FIG. 6
, into a lower-order n-bit counter
8
and a higher-order m-bit counter
9
.
In the first phase, the signal “fast” is activated, that is to say is at a logic “1”, with the result that a transmission gate
10
is open, while transmission gates
11
and
12
are inhibited and a transmission gate
13
is likewise open. As a result, an activation signal cen for the counters is present at the higher-order counter
9
directly via the transmission gate
10
, while the lower-order counter
8
is deactivated.
Thus, on account of the activation of the higher-order counter
9
, the counter
5
counts in distinctly larger steps compared with a normal operating mode, and the DLL approximates to the desired output phase faster. If the control signal “fast” is subsequently deactivated, that is to say changed to “0”, in a second phase, the activation signal cen is switched directly to the lower-order counter
8
via the transmission gate
12
, and the carry bit “count” of the lower-order counter
8
is switched through to the carry input cin of the higher-order counter
9
via the transmission gate
11
.
As a result, all bits are activated, and the counter
5
counts in correspondingly smaller steps. The DLL can then adjust the desired output phase with a higher temporal resolution.
Like
FIG. 5
,
FIG. 6
also shows the clock inputs clk_count and control inputs up for the counting direction of the counters
8
,
9
and output terminals “countvalue”, for supplying output signals count[n−1:0] for the counter
8
and respectively count[m+n−1:n] for the counter
9
.
In the prior art circuit configuration shown in
FIGS. 5 and 6
, problems arise when the control signal “fast” is deactivated at an arbitrary instant. Reference is had, in this regard, to FIG.
2
(
a
) which shows the profile of the clock signal clk_count, and to FIG.
2
(
b
) which illustrates the control signal “fast”, in the prior art circuit configuration. If the deactivation of the control signal “fast” almost or entirely coincides temporally with a change in the level of the clock signal, as is indicated by a double arrow
14
in
FIG. 2
, then instabilities can occur in the counter value countvalue, which causes the entire DLL to be in a state in which it can no longer adjust the desired phase angle of the internal clock signal Ti.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for the interference-free initialization of DLL circuits with fast lock, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which instabilities of counter values on account of the deactivation of a counter control signal are avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock, which comprises:
a delay line receiving an external clock signal and outputting an on-chip clock signal;
a phase detector, a filter, a counter device and an analog/digital converter connected to and driving the delay line for synchronizing the on-chip clock signal with the external clock signal;
the counter device having at least one higher-order counter and a lower-order counter each triggered by a counter clock signal and alternatively activatable and deactivatable with a control signal for shortening a time taken to adjust the delay locked loop;
wherein the control signal is converted into a delayed contro
Höhler Rainer
Von Borcke Mathias
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Vo Don N.
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