Circuit configuration for synchronous clock generation of at lea

Details Circuit configuration for synchronous clock generation of at lea Circuit configuration for synchronous clock generation of at lea

1994-11-16

1995-11-21

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

327155, 327295, H03K 1900, H03L 700

Patent

active

054690838

ABSTRACT:
A circuit configuration for synchronous clock generation of at least two clock signals, includes an enable stage for receiving a clock signal and enabling the clock signal under the control of an enable signal. A branching stage for receiving the enabled clock signal from the enable stage generates at least two clock signals from the enabled clock signal. Logic and/or driver stages are each connected downstream of the branching stage for receiving a respective one of the clock signals generated by the branching stage. Each of the logic and/or driver stages has an output at which a respective output clock signal can be picked up. Amplifiers are each connected to the output of a respective one of the other stages and are associated with a respective one of the output clock signals, for detecting edges of the output clock signals. A logic array connected to the amplifiers logically links the output signals generated by the amplifiers. The logic array generates the enable signal for controlling the enable stage.

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patent: 5122679 (1992-06-01), Ishii et al.
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Patent Abstracts of Japan, vol. 13, No. 433 (E-824) Sep. 27, 1989 & JP-A-1-161912 (Toshiba) Jun. 26, 1989.

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