Circuit configuration for reducing disturbances due to a switchi

Details Circuit configuration for reducing disturbances due to a switchi Circuit configuration for reducing disturbances due to a switchi

1998-09-25

2000-05-30

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 87, 326 83, H03K 1716

Patent

active

060694866

ABSTRACT:
A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.

REFERENCES:
patent: 5329175 (1994-07-01), Peterson
patent: 5424653 (1995-06-01), Folmsbee et al.
patent: 5781050 (1998-07-01), Russell
"Digital MOS Integrated Circuits II", edited by Mohamed I. Elmasry, IEEE Solid-State Circuits Council, pp. 385-392.

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