Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-07-25
2004-11-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06813200
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a circuit configuration for reading out a programmable link.
Large scale integrated semiconductor memory circuits normally have a multiplicity of memory cell arrays which in turn include a multiplicity of individual memory cells. During customary mass production of such integrated semiconductor memories it is no longer possible for all the memory cells to be produced without any defects. Therefore, a predetermined number of redundant memory cells are normally produced concomitantly on each semiconductor memory chip.
Memory cell arrays are normally structured in matrix form and include memory cells that are configured in columns and rows and can be selected, read from, and written to using so-called word lines and bit lines. The memory cells are configured at the crossover points between the word lines and the bit lines.
During the production of semiconductor memories, tests are usually carried out in order to identify the defective memory cells and to replace them by redundant memory cells. During these memory tests, it is normally the case that, in a memory cell array, entire word lines or entire bit lines or a plurality of word lines or bit lines are always used as the smallest redundant unit.
The assignment of which redundant element replaces which defective element in the memory cell array is defined by using programmable links, the so-called fuses. Fuses are non-volatile memory elements that can be programmed by feeding in an energy pulse. Each redundant element, that is to say each bit line, word line or interconnection of a plurality of word lines or bit lines has a bank of programmable links assigned to it—the so-called fuse bank. Each of these memory banks includes a so-called master fuse indicating that the associated redundant element is used as a repair element. The address of the element to be repaired in the memory cell array is coded with the remaining programmable links of the memory bank.
As soon as a memory cell array with the programmed address to be repaired is intended to be accessed in normal operation, the correspondingly assigned redundant element is accessed instead of a defective element. For this purpose, during each memory access, the desired memory address must be compared with all the programmed addresses of the redundant elements. Since access to the programmable links can only be carried out comparatively slowly, when the memory module is switched on or started up, all the programmable links are read out and the address data stored in the programmable links are stored in respectively assigned volatile memory cells. Such volatile memory cells are normally designed as a so-called latch or flip-flop. The actual address comparison which is effected during each memory access is then carried out with the copy of the address which is stored in the volatile memory cells.
The one-time programming of the programmable links during the abovementioned memory test during the production of the integrated memory module is normally effected such that, in a first step, the address data to be programmed are used to mark the electrical links to be programmed and, in a subsequent method step, the marked programmable links are programmed with an energy pulse, for example by applying a current surge or a voltage pulse.
It is known to perform the flagging of the links to be programmed by storing a corresponding datum in a volatile memory cell assigned to the respective programmable link. For this purpose, all the volatile memory cells can be coupled to a shift register, and the information about the programmable links to be programmed is shifted serially into the shift register. What is problematic, however, is that this shift register circuit has a comparatively large amount of components and a comparatively large chip area requirement. Moreover, comparatively elaborate wiring results on the chip. The comparatively high outlay is particularly problematic since a few hundred or even a few thousand redundant elements are provided on a semiconductor memory chip having a storage capacity of, for example, several hundred megabits.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for reading out a programmable link which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the present invention to specify a circuit configuration for reading out a programmable link, which enables assigned programmable links to be marked during a memory test with a low outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for reading out a programmable link. The circuit configuration includes a volatile memory cell having an input coupled to the programmable link for reading out and buffer storing a programmed value. The volatile memory cell has an output. The circuit configuration also includes an address input for feeding an address value and a combination unit having a first input connected to the address input, a second input connected to the output of the volatile memory cell, and an output for providing a hit signal if the programmed value and the address value correspond. The circuit configuration includes a switch for coupling the address input to the input of the volatile memory cell for storing the address value in the volatile memory cell. The switch has a control input. The circuit configuration includes a device for programming the programmable link and a control circuit having an input coupled to the output of the combination unit. The control circuit has an output coupled to the control input of the switch and to the device for programming. The control circuit provides an activation signal.
In accordance with the present principle, the address values present at address inputs are used directly for flagging the programmable links to be programmed. In this case, as a result of corresponding address values being fed to the address input, a hit signal can be generated in a targeted manner at the output of the combination unit in order to select a specific memory bank with a multiplicity of links to be programmed. The hit signal drives the control circuit in such a way that, in a test operating mode, the address input is switched through to the volatile memory cell by a switch.
The switch advantageously enables the use of an address line in order to program the volatile memory cell, which is preferably embodied as a so-called latch.
As a result of combining the circuit configuration for reading out a programmable link with a switch between the address input and the volatile memory cell and the control circuit for driving the switch in a test operating mode, it is possible, in accordance with the present principle, to use the address values present at address inputs for programming the programmable link. The present principle makes it possible to dispense with a shift register for flagging the programmable links and can be realized with a significantly lower outlay on circuitry than a shift register.
The circuit inventive configuration can be used in dynamic semiconductor memories, so-called dynamic random access memories (DRAMS).
In accordance with the present principle, it is also possible for the address values of the address inputs not to be used directly for setting or resetting the assigned volatile memory cells, but rather for a hit signal to be generated in a targeted manner depending on an applied address value.
The volatile memory cell is preferably designed as a so-called latch.
The control circuit preferably includes a memory cell for storing the activation signal depending on a hit signal present.
The control circuit preferably has a further signal input, at which a set signal indicating a test operating mode is fed in. The activation signal is accordingly provided by the control circuit when a test operating mode is activated and when a hit signal indicates correspondence between prog
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Locher Ralph E.
Mayback Gregory L.
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