Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-11
2001-09-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S200000
Reexamination Certificate
active
06288939
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration containing memory devices, which contain programmable elements and volatile memory elements, for monitoring the states thereof.
For repairing faulty memory cells, integrated circuits, particularly integrated memories, have redundant word lines or redundant bit lines, which can replace regular lines containing faulty memory cells on an address basis. In this case, the integrated memory is, by way of example, tested by a self-test device, and the redundant elements are subsequently programmed. A redundancy circuit then has programmable elements, for example in the form of electrical fuses, which are used for storing the address of a line that is to be replaced. The electrical fuses are electrical connection elements whose line resistance can be varied, for example at the end of the process of manufacturing the integrated circuit, by a so-called burning voltage.
U.S. Pat. No. 5,313,424 discloses an integrated memory having a self-repair function. A self-test unit tests the memory cells in the memory and then stores the address of faulty word lines in an appropriate address register. An activation signal with a high potential level is then supplied to the memory from outside, whereupon the severable electrical connection elements (fuses), which are a component part of a redundancy circuit, are destroyed to code the faulty word addresses stored in the address register. In this context, the fuses are destroyed by a high current that causes them to melt.
A further circuit configuration, disclosed in Published, Non-Prosecuted German Patent Application DE 198 43 470 A1, allows external analysis of the faults established. A memory unit for storing the address ascertained by the self-test unit has an output that is connected to a corresponding output of the circuit configuration for outputting the respectively stored address. Hence, if required, the manufacturer of the integrated circuit can establish whether faults have been established during the memory self-test and whether self-repair has been carried out. In addition, the manufacturer can establish the address of the faults established.
A volatile memory unit, such as an address register or address latch, can easily have information written to it by a self-test unit, since no voltages exceeding the normal signal level of the memory or large currents are required for this. The provision of a further, nonvolatile memory unit has the advantage that the memory self-test does not need to be repeated every time the volatile memory unit has lost the address stored in it (for example after the supply voltage has been turned off). If only one volatile memory unit were provided, the address of the normal units to be replaced would otherwise have to be established once again by the self-test (for example whenever the memory is initialized). The address is therefore permanently stored in the nonvolatile memory unit in a further step. To restore the memory content of the volatile memory unit, for example whenever the memory is initialized after the supply voltage is applied, the address stored in the nonvolatile memory unit then needs to be transferred to the volatile memory unit.
Particularly when electrical fuses are used, the burning procedure carried out to program the fuses does not always take place reliably. The transfer procedure carried out to restore the memory content of the volatile memory unit can therefore not always be completed reliably. The result of this is, by way of example, an incorrectly stored address in the volatile memory unit after the transfer procedure. It is therefore desirable to check whether the respective electrical fuse has been set such that the volatile memory element can reconstruct the originally stored information again from the state of the relevant fuse.
In the Published, Non-Prosecuted German Patent Application DE 198 43 470 A1, the output of the first volatile memory unit therein is a serial output for outputting the stored address bit by bit. The advantage of this is that the memory unit has only this one output. However, an associated serial shift procedure results in that the information stored in the volatile memory elements is first erased and, in the case of a shift register with feedback, the originally contained information is restored only after a complete cycle. By contrast, in the case of the present application, it is important for the information stored in the respective volatile memory element to be retained permanently in order to be able to compare it reliably at a later instant with the state reconstructed from the fuse.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for monitoring states of a memory device which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which states of volatile memory elements can be read such that stored information is retained, and which can be checked to determine whether the information originally intended for the volatile memory element can be reconstructed from the state of the associated programmable element.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, containing:
a plurality of memory devices each including:
a programmable element having a first output and a second output;
a volatile memory element having an input and an output; and
a switching device connecting the first output of the programmable element to the input of the volatile memory element; and
at least one output terminal for outputting a state of the programmable element and a state of the volatile memory element; and
a selection circuit connected to the memory devices, the memory devices being individually addressed via the selection circuit to output states of the programmable element and of the volatile memory element.
The circuit configuration has memory devices, each containing the programmable element and the volatile memory element. To store the state of the programmable element in the volatile memory element, for each memory device, an output of the programmable element is connected to an input of the volatile memory element. To check the respective state of the volatile memory element and of the programmable element, the respective memory device has at least one output for outputting the desired state. The memory devices can be addressed individually and directly via the selection circuit to output the states of the respective memory device. Direct access to the respective memory device with its volatile memory element does not change the information in the latter during a read procedure. In addition, direct access to the respective memory device enables faster and more targeted access in comparison with a read method using a serial shift register. On the other hand, it is naturally also possible to write information to the respective memory device directly.
In this manner, a plurality of states of the memory device can also be read in parallel or serially without any significant increase in the additional circuit complexity required for this. If the assessment of the states of the volatile memory element and of the programmable element in the same memory device uncovers a fault in the programming already carried out for the programmable element, suitable measures can be used to react to this. Such a measure may be, by way of example, a new programming procedure for the same programmable element or may also involve the appropriate circuit part being marked as faulty.
In one development of the invention, the circuit configuration has a further volatile memory element, which is connected to the output for outputting the state of the programmable element in one of the memory devices in order to store the state of the programmable element temporarily. The output of the further volatile memory element and the output for outputting the state of the volatile memory element in the memory device which is to be chec
Kaiser Robert
Schamberger Florian
Elms Richard
Greenberg Laurence A.
Infineon Technologies
Lerner Herbert L.
Nguyen Hien
LandOfFree
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