Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-01
2003-12-16
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S336000, C257S337000, C257S341000
Reexamination Certificate
active
06664590
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for load-relieved switching having a bridge circuit with at least two-controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches. The circuit configuration also has an inductive element that is connected to the output terminals of the bridge circuit.
The article by Leo Zaro et al. “High-Voltage MOSFET Behavior in Soft-Switching Converters: Analysis and Reliability Improvements”, in Proceedings INTELEC, 1999, pages 30-40, describes a generic circuit for voltage-relieved switching that is designed as a full-bridge circuit with four power switches.
In power switches, it is possible, in principle, to distinguish between two different types of power loss. First, there is the power loss during the “on phase”, during which the power switch is switched on or controlled at a low impedance. These losses essentially result from the voltage that is dropped as a result of a current flow in the channel region of the semiconductor switch. Second, there also exist switching losses that are caused by the reciprocal switch-on and -off operation of the power switch, that is to say when a high current density and a high voltage are simultaneously present at the power switch. However, these losses are incurred only during very short time intervals during switch-on and during switch-off. However, as the switching frequency rises and/or as the power to be switched increases, these switching-dictated losses increasingly gain in importance for the total power loss balance.
Therefore, development turns toward circuit concepts that reduce such switching losses by a suitable choice of the switching conditions. One such concept is what is referred to in the relevant technical literature as “Zero Voltage Switching” (ZVS). The corresponding circuits are also referred to as resonant circuits or as circuits for zero voltage or voltage-relieved switching. In the case of such circuit configurations, the semiconductor switch is switched on or off at a point in time at which no voltage or only a small voltage is present at the switch. In this case, the semiconductor switch must ideally accept no commutation current at all from other circuit sections, as a result of which, switch-on losses can be disregarded here. During the switch-off operation, care is taken to ensure that the voltage rise at the component is delayed in such a way that the maximum current density and the maximum voltage are not present simultaneously at the power switch at any point in time.
The basic construction and the method of operation of a circuit configuration for load-relieved switching that is designed as a PWM converter are described in detail in the article by Zaro et al. cited in the introduction. The circuit topology described by Zaro et al. in
FIG. 1
therein includes a full bridge with four MOSFETs S
1
-S
4
and an inductive element in the center of the bridge. What is problematic in this case is that, when very high powers will be switched, using conventional MOSFETs for such circuit topologies leads to the functional failure of the circuit.
This destruction mechanism will be illustrated with reference to
FIGS. 9 and 10
.
FIG. 9
shows the temporal profile of the drain-source voltage VS
2
at the MOSFET S
2
and
FIG. 10
shows a diagrammatic partial section through a vertical MOSFET that is typically used for this. The destruction mechanism is caused by an injection of storage charge into the drift region of the reverse-biased MOSFET S
2
, which is dissipated only very slowly (phase a). During a subsequent turn-off (phase b) of the MOSFET S
2
—for example after a few microseconds—the storage charge still present in the volume of the drift region
110
leads to an excessively increased hole current (phase c) to the source terminal, which results in a voltage drop in the body zone
113
of the MOSFET. If the voltage drop VS
2
, at the instant t
crit
, exceeds the switch-on voltage of a parasitic diode at the pn junction between the base zone and the drain zone, then the parasitic bipolar transistor that is always inherent in a MOSFET and whose emitter, base and collector are formed by the source zone
114
, base zone
113
and drain and drift zone
110
,
107
is undesirably switched on (phase d). This undesirable switch-on of the parasitic bipolar transistor is also referred to as the latch-up effect or the “second breakdown”. In such a case, the reverse voltage of the semiconductor component falls very rapidly, which typically leads to the direct destruction of the semiconductor component itself. This latch-up effect is intensified by the fact that the voltage breakdown, promoted by the curvature of the pn junction between the base zone
113
and the drift zone
110
, generally occurs at the edge of the base zone
113
, since the hole current flows from the volume of the semiconductor body principally via the lateral pn junction into the base zone
113
, so that the high current density arises there.
In the article cited in the introduction, Zaro et al. therefore arrive at the conclusion that semiconductor components in ZVS circuit topologies that have a high storage charge Qrr in the reverse operation and a correspondingly long recovery time trr are affected by precisely the destruction mechanism mentioned.
FIG. 11
shows the temporal profile of the load current curve of a conventional MOSFET, which is used to define the storage charge Qrr and the recovery time trr. The storage charge Qrr results from:
Qrr
=
∫
t10
t20
Ir
(
t
)
ⅆ
t
,
in other words the storage charge Qrr is the total quantity of the charge in the time period between t
10
and t
20
. The instant t
20
is produced by interpolating the straight line through the points I
r,90%
=0.9 * I
rrm
and I
r,10%
=0.1 * I
rrm
, where I
rrm
denotes the minimum load current Ir. The recovery time is then defined as:
trr=t
20
−
t
10
.
In their article, the authors recommend that transistors with high storage charge Qrr and long recovery time trr not be used in ZVS circuit topologies, in particular in ZVS bridge circuits. This recommendation by the authors that is expressed in the cited article has been followed hitherto by manufacturers and customers of such circuit configurations, for example, those in the equipment industry for telecommunications products. The result is that nowadays power transistors with high storage charge Qrr and high recovery time trr are scarcely used in ZVS circuits.
One possibility for alleviating the destruction mechanism is to use semiconductor components in which irradiation is performed in order to reduce the charge carrier lifetime. On account of the recombination centers distributed in the space charge zone of the semiconductor component, this measure leads to faster discipation of the charge carriers injected into the drift zone even when no electric field is present. However, the irradiation destroys the semiconductor crystal, which adversely affects the on resistance RDS
on
, the blocking capability or the threshold voltage of the semiconductor component, depending on the type of irradiation. The impairment, i.e. the increase in the on resistance RDS
on
, should be avoided, however, particularly in the case of power components, since high on resistances result in a high power loss in the switched-on state of the semiconductor component. Furthermore, in the case of a short duration between the forward biasing of the current and its turn-off, it does not suffice, even with using the irradiation technique, to dissipate the storage charge contained in the drift zone in such a way that a latch-up effect as described above is avoided. Therefore, the irradiated semiconductor components mentioned are suitable only to a limited extent for ZVS circuit topologies that have to be designed for very high reverse voltages.
Thus, ZV
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Ngo Ngan V.
Stemer Werner H.
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