Circuit configuration for identification of integrated semicondu

Details Circuit configuration for identification of integrated semicondu Circuit configuration for identification of integrated semicondu

1992-09-16

1993-06-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

365 96, 3652257, 36518912, G11C 1140

Patent

active

052220435

ABSTRACT:
A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements each having an output. A parallel-serial shift register has n parallel inputs each being connected to a respective one of the outputs of the n programmable elements, a data output, a control input for transferring electrical states of the programmable elements into the parallel-serial shift register, and a clock input for controlling a shift function of the parallel-serial shift register as a function of a clock signal to be applied to the clock input.

REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto

Affiliated with

Also associated with

Rating

Circuit configuration for identification of integrated semicondu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit configuration for identification of integrated semicondu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit configuration for identification of integrated semicondu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1444837