Circuit configuration for generating an interrupt signal for a m

Details Circuit configuration for generating an interrupt signal for a m Circuit configuration for generating an interrupt signal for a m

1998-09-09

2000-08-08

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Interrupt processing

Programmable interrupt processing

710 48, 710260, 709300, G06F 948, G06F 954

Patent

active

061015717

ABSTRACT:
A circuit configuration for generating an interrupt signal for a microprocessor includes a multiplicity of signal generating circuits that are connected to one another via a logic combination element. Each of the signal generating circuits is configured to activate an intermediate signal when a specific event occurs for an assigned input signal. On the input side, each signal generating circuit has a respective edge detector for detecting rising and falling edges, which are routed via demultiplexers and two further logic combination elements to the set and reset inputs of a flip-flop. The structure can be programmed flexibly and detects, by hardware, an interrupt state with no additional computation loading on the microprocessor.

REFERENCES:
patent: 3771146 (1973-11-01), Cotton et al.
patent: 4410938 (1983-10-01), Higashiyama
patent: 5784625 (1998-07-01), Walker
patent: 5802153 (1998-09-01), Sridhar et al.
patent: 5828891 (1998-10-01), Benayoun et al.

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