Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-01
2004-03-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S312000, C327S566000, C327S581000
Reexamination Certificate
active
06700149
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for forming an MOS capacitor with a low voltage dependence.
In MOS circuits (metal oxide semiconductor circuits), it is known to realize capacitors using MOS transistors. In this case, the capacitors are formed by a gate terminal, a gate oxide and a substrate. Compared with polysilicon/oxide/polysilicon capacitors, polysilicon/oxide/metal capacitors, and metal/oxide/metal capacitors, the MOS capacitor requires a lower area and has lower fabrication costs. The disadvantage resides in the voltage dependence of the capacitance profile, which limits the voltage range over which the MOS capacitor can be used.
Published European Patent Application EP 0 720 238 discloses a circuit configuration in which this voltage dependence is reduced using two series-connected MOS transistors. The transistors that are used are each operated in accumulation or inversion. For small operating voltages, however, this principle cannot be used or can only be used to a limited extent. In present CMOS processes, moreover, the gate capacitance is also voltage-dependent in accumulation and inversion.
The Digest of Technical Papers for the 1996 Symposium on VLSI circuits, pages 152 and 153, “Novel Design Techniques for High-Linearity MOSFET-Only Switched-Capacitor Circuits”, Yoshizawa, Temes et al., discloses “parallel compensation” for MOS transistors in which all that is present is a parallel circuit of two series-connected MOS transistors that are each operated in accumulation or inversion.
U.S. Pat. No. 5,801,411 discloses an integrated capacitor structure that is constructed from a combination of MOS transistors that are connected in parallel and operated in depletion. This structure is designed for use with small operating voltages. The relatively large area required by the transistors, and thus by the entire arrangement is disadvantageous.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for forming a MOS capacitor which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a circuit configuration for forming an MOS capacitor that requires only very small operating voltages to ensure a sufficient functionality of the circuit, and that can be realized in a particularly space-saving manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for forming an MOS capacitor with a low voltage dependence. The circuit configuration includes: a first MOS transistor having a drain terminal and a source terminal; and a second MOS transistor having a drain terminal and a source terminal. The drain terminal of the first MOS transistor is connected to the source terminal of the first MOS transistor. The drain terminal of the second MOS transistor is connected to the source terminal of the second MOS transistor. The first MOS transistor is a short-channel transistor having a channel length not greater that 1 &mgr;m. The second MOS transistor is a short-channel transistor having a channel length not greater that 1 &mgr;m.
In accordance with an added feature of the invention, the first MOS transistor and the second MOS transistor are operated in depletion.
In accordance with an additional feature of the invention, the first MOS transistor having a given channel type, a bulk terminal, and a gate; the second MOS transistor having the given channel type, a bulk terminal, and a gate; and the first MOS transistor is connected to the second MOS transistor in either a first manner or a second manner. In the first manner, the bulk terminal of the first MOS transistor and the bulk terminal of the second MOS transistor define interconnected terminals that are connected together. In the second manner, the gate of the first MOS transistor and the gate of the second MOS transistor define interconnected terminals that are connected together. The first MOS transistor and the second MOS transistor are reverse-connected in series. The first MOS transistor has a depletion region that is widened by a first potential difference. The second MOS transistor has a depletion region that is widened by a second potential difference. The first potential difference is connected between the interconnected terminals (the interconnected terminals are dependent upon whether the transistors are connected in the first manner or the second manner) and the drain terminal of the first MOS transistor. The second potential difference is connected between the interconnected terminals and the drain terminal of the second MOS transistor.
In accordance with a further feature of the invention, there is provided, a first terminal and a second terminal; the first MOS transistor having a bulk terminal, and a gate; the second MOS transistor having a bulk terminal, and a gate; the first MOS transistor and the second MOS transistor being reverse-connected in parallel; the bulk terminal of the first MOS transistor being connected to the gate of the second MOS transistor and to the second terminal; the bulk terminal of the second MOS transistor being connected to the gate of the first MOS transistor and to the first terminal; the first MOS transistor having a depletion region being widened by a first potential difference; the second MOS transistor having a depletion region being widened by a second potential difference; the first potential difference being connected between the drain terminal of the first MOS transistor and the bulk terminal of the first MOS transistor; and the second potential difference being connected between the drain terminal of the second MOS transistor and the gate terminal of the second MOS transistor.
The invention essentially consists in the providing a circuit configuration for forming an MOS capacitor with transistors designed as so-called short-channel MOS transistors whose channel length is less than or equal to 1 &mgr;m, as a result of which, in addition to the intrinsic capacitances, extrinsic capacitances are also used for forming the MOS capacitor. The utilization of the extrinsic capacitances is beneficial primarily in the case of compensated MOS capacitors that are operated in depletion. This means, in particular, for compensation circuits operated in depletion, a considerably reduced outlay on area.
Furthermore, the circuit configuration provides advantages over polysilicon/oxide/polysilicon capacitors, polysilicon/oxide/metal capacitors, and metal/oxide/metal capacitors in view of their area and cost-intensive additional process layers. Consequently, it is possible to fabricate, in particular, analog circuits for low supply voltages together with digital circuits as a “single-chip solution” inexpensively in a single process.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for forming a MOS capacitor with a lower voltage dependence and a lower area requirement, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 4268951 (1981-05-01), Elliott et al.
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patent: 5576565 (1996-11-01), Yamaguchi
patent: 5801411 (1998-09-01), Klughart
patent: 5926064 (1999-07-01), Hariton
patent: 6028473 (2000-02-01), Kamei et al.
patent: 6472233 (2002-10-01), Ahmed et al.
patent: 198 43 482 (1999-08-01), None
patent: 0 290 857 (1988-11-01), None
patent: 0 354 193 (1990-02-0
Sauerbrey Jens
Schmitt-Landsiedel Doris
Tille Thomas
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