Circuit configuration for a programmable nonvolatile memory and

Details Circuit configuration for a programmable nonvolatile memory and Circuit configuration for a programmable nonvolatile memory and

1998-08-31

1999-08-31

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

36518509, 365200, 36518522, 371 211, G11C 1300

Patent

active

059462493

ABSTRACT:
A circuit configuration for a programmable nonvolatile memory having memory cells organized in rows and columns, includes a programming circuit which contains a first device for testing purposes that applies a programming current to a first predetermined number of memory cells in parallel for a first predetermined time period. During a second predetermined time period, the device thereupon connects a second predetermined number, which is greater than the first number, in parallel an applies the programming current to them. A method is provided for operating the circuit configuration.

REFERENCES:
patent: 5416741 (1995-05-01), Ohsawa
patent: 5548596 (1996-08-01), Tobita
patent: 5581510 (1996-12-01), Furusho et al.
patent: 5610861 (1997-03-01), Sim
patent: 5784323 (1998-07-01), Adams et al.
patent: 5809225 (1998-09-01), Ohsawa et al.
Japanese Patent Abstract No. 61165898 (Shinichi), dated Jul. 26, 1986.
Japanese Patent Abstract No. 63153797 (Koichi), dated Jun. 27, 1988.

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