Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-12-10
2003-09-23
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S158000, C365S209000
Reexamination Certificate
active
06625076
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to a method and a circuit configuration for evaluating the information content of a memory cell, preferably of a MRAM memory cell, or of a corresponding memory cell array.
Magnetoresistive random access memories (MRAMs) are memories in which data can be stored under an address and also be read out again. The memories generally have one or more memory cells (memory cell array), the memory effect residing in the magnetically variable electrical resistance of the memory cell or memory cells. MRAM memory cells usually have a layer sequence containing a combination of ferromagnetic materials and an insulator layer respectively lying in between. The insulator layer is also referred to as a tunnel dielectric.
Depending on the magnetization state of the memory cell, the magnetization directions in the magnetic layers can be oriented in a parallel or anti-parallel manner. The memory cell has a different electrical resistance depending on the magnetization direction in the magnetic layers. In this case, a parallel magnetization direction leads to a lower electrical resistance in the memory cell, while an anti-parallel magnetization direction leads to a higher resistance.
The insulator layer may have a thickness of about 2 to 3 nm, for example. The electronic conductivity through the layer system is essentially determined by a tunnel effect through the insulator layer. Variations in the tunnel insulator thickness lead to great variations in the conductivity since the insulator thickness influences the tunneling current approximately exponentially.
When such a memory cell is written to, it is done by an electric current. To that end, the memory cell is constructed in such a way that it has two-electrical conductors that cross one another. A layer sequence containing magnetic layers and a tunnel dielectric layer as described above is provided in each case at the crossover point of the electrical conductors. An electric current flows through the two conductors and in each case generates a magnetic field. The magnetic field acts on the individual magnetic layers. If the magnetic field strength is sufficiently large, the magnetic layers exposed to the field are subjected to a magnetization reversal.
The size of the magnetic field acting on the individual magnetic layers depends first on the size of the currents flowing through the two conductors, and second also on the spatial configuration of the respective magnetic layers with regard to the electrical conductors.
The current flowing through the conductors thus has the effect that the magnetization directions can change in individual magnetic layers. Depending on the magnitude of the impressed current, individual layers of the cell are subjected or are not subjected to a magnetization reversal.
If the memory cell is subsequently read or evaluated, this can be done, for example, by a corresponding programming operation. Therefore, such a high current is impressed into the electrical conductors of the memory cell that individual or a plurality of magnetic layers are subjected to magnetization reversal. If, in the event of a subsequent current measurement of the current through the cell or a voltage measurement correlated with the cell current, it is ascertained that the values have remained the same, this results in that the information content was actually already stored beforehand in the memory cell. In contrast, if the current value or voltage value changes, this results in that the information content of the memory cell has changed. As an alternative, it is also possible to detect a change in the information content by measuring the cell resistance.
If the cell is to be read, first the electrical cell resistance is measured. Published, European Patent Application EP 0 450 912 A2 describes a method for reading from an MRAM, in which an activation current is applied to the relevant memory cell, which current is directed in such a way that the magnetic field brought about by the current is directed oppositely to a common magnetization at the edges of the magnetizable memory medium.
The measured values are evaluated in corresponding evaluation circuits. In this case, the obvious approach is, in principle, the approach known from other types of memory, namely of comparing a measured current value, or a voltage value correlated therewith, with a defined reference value. The reference value is generally defined once before the beginning of the operation of the MRAM memory and applies to all the memory cells of the memory. The defined reference value functions as a threshold value which determines the information state of the memory cell depending on the state of the memory cell. If the evaluation circuit detects a current value or voltage value that lies above or below the defined reference value, the information content of the memory cell is inferred from this.
However, this form of evaluation of memory cells has a series of disadvantages. Thus, by way of example, the higher and lower currents or voltages must be sufficiently different from one another to allow reliable evaluation of the memory cell given appropriate positioning of the defined threshold. This is particularly difficult, however, since the changes in current or voltage and the resultant changes in resistance vary within limits of only about 10% and are therefore only relatively small. For this reason, the reference value must be fixed at a very precise value.
Since the MRAM memories usually contain quite a lot of memory cells, the so-called memory cell arrays, must be evaluated by a single evaluation circuit.
For technical fabrication reasons, however, it is not possible for the insulator layers in all the memory cells and between all the magnetic layers always to have exactly the same thickness. On account of these unpreventable variations in the insulator layer thickness, but also as a result of other technologically or physically governed parameter variations, variations in the cell resistance and thus also variations in the cell current can arise, which can prevent reliable evaluation of the memory cell information. For this reason, under certain circumstances, it is not possible to specify defined thresholds or reference values in order to be able to reliably evaluate all the memory cells of a predetermined memory cell array.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for evaluating the information content of a memory cell which overcomes the above-mentioned disadvantages of the prior art devices of this general type. In particular, the intention is to enable accurate and reliable evaluation of a memory cell or of a memory cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for evaluating an information content of a magnetoresistive random access memory (MRAM) memory cell. The circuit configuration contains a ground terminal, a line connected to the MRAM memory cell, and a component being either a resistor or a transistor connected as a diode. The component is connected between the ground terminal and the line. A first circuit branch is provided and has a first switch with a first terminal and a second terminal, the first terminal of the first switch is connected to the line. A second circuit branch is provided and has a second switch with a first terminal and a second terminal, the first terminal of the second switch is connected to the line and to the first terminal of the first switch. An evaluation unit is connected to the second terminal of the first switch and to the second terminal of the second switch. A first capacitor is connected between the second terminal of the first switch and the ground terminal. The first capacitor functions as a first buffer store for storing a first value measured from the MRAM memory cell and the first value is either a first current value or a first voltage value. After the first value is buffered stored, t
Thewes Roland
Weber Werner
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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