Circuit configuration and a method of testing storage cells

Details Circuit configuration and a method of testing storage cells Circuit configuration and a method of testing storage cells

1988-03-16

1990-09-11

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Testing

365203, 365190, 371 211, G11C 2900

Patent

active

049568191

ABSTRACT:
A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a "no fault" situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4603405 (1986-07-01), Michael
patent: 4742489 (1988-05-01), Hoffmann
patent: 4742490 (1988-05-01), Hoffmann
patent: 4752929 (1988-06-01), Kantz et al.

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