Circuit clustering during placement

Details Circuit clustering during placement Circuit clustering during placement

2006-08-14

2008-12-16

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07467368

ABSTRACT:
A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit design can be clustered by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed to minimize critical connections. The circuit design can be declustered to perform additional placer optimization tasks on the declustered circuit design.

REFERENCES:
patent: 5475830 (1995-12-01), Chen et al.
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6813754 (2004-11-01), Wu et al.
patent: 6957412 (2005-10-01), Betz et al.
patent: 7111262 (2006-09-01), Singh
patent: 7290239 (2007-10-01), Singh et al.
patent: 2004/0250226 (2004-12-01), Lin et al.
Donath, Wilm E.; “Placement and Average Interconnection Lengths of Computer Logic”; Circuits and Systems, IEEE Transactions on; vol. 26, Issue 4; Apr. 1979; pp. 272-277.
DeHon, Andre; “Balancing Interconnect and Computation in A Reconfigurable Computing Array” International Symposium on Field Programmable Gate Arrays Archive Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on FPGAs; 1999; pp. 69-78 [1-10].
Singh, Amit et al.; “Efficient Circuit Clustering for Area and Power Reduction in FPGAs”; International Symposium on FPGAs, 2002; Copyright Association for Computing Machinery; 8 pages.
Landman, B. S. et al.; “On a Pin Versus block Relationship for Partitions of Logic Graphs”; IEEE Transactions on Computers, vol. C-20, No. 12, Dec. 1971; pp. 1469-1479.
Russo, R. L. et al.; “A Computer-Based-Design Approach to Partitioning and Mapping of Computer Logic Graphs”; Proceedings of the IEEE; vol. 60; Issue 1; Jan. 1072; pp. 28-34.
Parthasarathy, G. et al.; “Interconnect Complexity-Aware FPGA Placement Using Tent's Rule”; Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction; Mar. 2001; pp. 115-121.
Singh, Amit et al.; Interconnect Resource-Aware Placement for Hierarchical FPGAs; Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design; Nov. 2001; pp. 132-136.
Marquardt, Alexander et al.; “Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density”; Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable; pp. 37-46.

Affiliated with

Also associated with

Rating

Circuit clustering during placement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit clustering during placement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit clustering during placement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4027172