Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-01
2004-02-10
Smith, Matthew (Department: 2763)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06691296
ABSTRACT:
This application is based on applications Nos. 10-021089 and 10-364143 filed in Japan, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a design aiding apparatus for designing a circuit board with a low noise level, a design aiding method, and a storage medium storing a design aiding program.
2. Description of the Prior Art
With the development of multilayer printed circuit boards, circuit boards that include not only signal wiring surfaces but also solid conductor surfaces (planes), such as a 0-volt ground plane, a 5-volt power plane and a 12-volt power plane, have increasingly been used in recent years.
A CAD apparatus for such multilayer circuit boards is disclosed in Japanese Laid-Open Patent Application 9-26979. In this CAD apparatus, the geometry of each subplane of a power plane is generated based on data inputted by a designer for specifying a voltage level of each component and an approximate boundary line between each two component groups. More specifically, once the designer has inputted a voltage level of each component and roughly specified a boundary line between each two component groups which have different voltage levels, the CAD apparatus detects intersection points between the specified boundary lines and the peripheral lines of a board, forms areas (closed loops) which each enclose a component group, and calculates the geometry of a subplane (expressed by a coordinate string showing a continuous line created by inwardly offsetting a closed loop) for each closed loop. Thus, only by specifying voltage levels of components and rough boundary lines between component groups, the designer can design the geometry of each subplane which differs in voltage level. In addition, even when components are randomly placed irrespective of their voltage levels, the complex geometries of subplanes can be obtained by generating closed loops along boundary lines between component groups.
In a circuit board containing high-speed signal lines, a high-speed signal normally takes a feedback path of the lowest impedance. In the case of a multilayer circuit board, a signal of a high-speed signal line routed on a signal layer mostly takes a feedback path formed by projecting the signal line onto a plane nearest to the signal layer. This technique is described in detail in Mark I. Montrose (1996)
Printed Circuit Board Design Techniques for EMC Compliance
, IEEE No. PC5595, and Howard W. Johnson & Martin Graham (1993)
High
-
Speed Digital Design: A Handbook of Black Magic
, PTR Prentice-Hall.
For suppressing undesired electromagnetic waves in designing a high-speed signal rigid circuit board, a printed circuit board designing method is disclosed in Japanese Laid-Open Patent Application 6-203102, while a printed circuit board, a printed circuit board designing method and a wiring pattern generating apparatus for a printed circuit board are disclosed in Japanese Laid-Open Patent Application 9-186465.
In the printed circuit board designing method disclosed in Japanese Laid-Open Patent Application 6-203102, each component block is placed so that high-frequency digital signal lines can be linearly routed between each two component block either in the X or Y direction on a signal layer, and the appearance of cutlines orthogonal to the direction of the signal lines is prohibited in an area formed by projecting the signal lines onto a power/ground layer nearest to the signal layer. By doing so, radiated electromagnetic noise can be reduced.
In the printed circuit board designing method disclosed in Japanese Laid-Open Patent Application 9-186465, two signal patterns are grouped as one in a printed circuit board composed of a signal layer, a power layer and a ground layer. Vias on two signal patterns of the same group are placed closely so that the signal patterns are insulated from each other, while vias on two signal patterns of different groups are placed with a space larger than the sum of the clearance diameter and the signal pattern width. By setting a clearance around each via hole in the above arrangement, a feedback path of a signal pattern is routed in the vicinity of an area formed by projecting the signal pattern onto the power/ground layer, with it being possible to reduce radiated electromagnetic noise caused by the signal pattern and a largely detoured feedback path.
However, the multilayer circuit board CAD apparatus of Japanese Laid-Open Patent Application 9-26979 lacks efficiency on the ground that the designer has to manually input boundary lines between component groups of different voltage levels. Besides, to connect components of a high-speed circuit group to one subplane adversely affects other component groups.
Although the printed circuit board designing method of Japanese Laid-Open Patent Application 6-203102 is effective in suppressing radiated electromagnetic noise, it is necessary to place component blocks in consideration of routing directions of high-speed signal lines and to route feedback paths in areas parallel to signal lines in consideration of directions of the signal lines and positions of via holes. Thus, this method has difficulties in designing a circuit board under the above constraints.
Also, the printed circuit board designing method of Japanese Laid-Open Patent Application 9-186465 fails to sufficiently suppress electromagnetic noise, since a signal of a signal line still takes an alternative path to avoid non-conductor areas around via holes directly below the signal line.
SUMMARY OF THE INVENTION
In view of the above problems, the present invention aims to provide a design aiding apparatus, a design aiding method and a storage medium storing a design aiding program that enable efficient design of a circuit board while suppressing electromagnetic noise and adverse effect caused by high-speed circuit blocks on other circuit blocks, without concern for design restrictions, such as placement of component blocks in consideration of directions of high-speed signal lines and routing of feedback paths in consideration of directions of signal lines and positions of via holes.
To fulfill the above object, the present invention is a design aiding apparatus for aiding placement of any of components, conductors and vias in a multilayer circuit board which includes at least one signal layer and at least one layer that is one of a power layer and a ground layer, the design aiding apparatus including: a routing path area generating unit for generating a routing path area on at least one signal layer or at least one layer that is one of a power layer and a ground layer, the routing path area partly including one of a signal line routed on a signal layer and a feedback path of a current which flows over a signal line routed on a signal layer; and a position calculating unit for calculating, based on the generated routing path area, one of a position at which any of components, conductors and vias is to be placed and a position at which any of components, conductors and vias is prohibited to be placed, to minimize an area enclosed by a loop formed by a current which flows over a signal line and a feedback path corresponding to the signal line.
With this construction, an area enclosed by a loop formed by a current that flows over a signal line and a feedback path corresponding to the signal line can be minimized by determining where any of components, conductors and vias is to be placed or where any of components, conductors and vias is prohibited to be placed, based on a routing path area set on a signal, power, or ground layer. Accordingly, a circuit board that has a low noise level can be designed with efficiency.
The above object can also be fulfilled by a design aiding apparatus for aiding placement of vias in a multilayer circuit board which includes at least one layer that is one of a ground layer and a power layer and at least one signal layer on which at least one conductor that interconnects terminals of respective components is placed, the design aiding appar
Fukumoto Yukihiro
Nakayama Takeshi
Saito Yoshiyuki
Uemura Hirokazu
Kik Phallaka
Matsushita Electric - Industrial Co., Ltd.
Smith Matthew
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