Circuit arrangement with at least four transistors, and method f

Details Circuit arrangement with at least four transistors, and method f Circuit arrangement with at least four transistors, and method f

1998-08-21

2000-05-09

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326119, 326121, 326101, 326102, 326103, 257329, 257369, H03K 19094, H01L 2976

Patent

active

060609117

ABSTRACT:
In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.

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T. Mizuno et al, IEDM Technical Dig., (1996), Experimental Study of Carrier Velocity Overshoot in Sub-0.1 .mu.m Devices, pp. 109-112.
IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991, H. Takato et al, Impact of Surround Gate Transistor (SGT) for Ultra-High-Density LSI's, pp. 573-578.

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