Circuit arrangement for verifying data stored in a random access

Details Circuit arrangement for verifying data stored in a random access Circuit arrangement for verifying data stored in a random access

1990-02-02

1991-09-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 371 212, G11C 1908, G11C 2900

Patent

active

050460471

ABSTRACT:
A circuit arrangement comprising, for each bit location in a column of a RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into a bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit. The result is stored in the shift register, which can be down-loaded for analysis.

REFERENCES:
patent: 3813032 (1974-05-01), King
patent: 4661930 (1987-04-01), Tran
patent: 4669061 (1987-05-01), Bhavsar
patent: 4715034 (1987-12-01), Jacobson
patent: 4849973 (1989-07-01), Kubota
patent: 4926424 (1990-05-01), Maeno

Affiliated with

Also associated with

Rating

Circuit arrangement for verifying data stored in a random access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement for verifying data stored in a random access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for verifying data stored in a random access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1014381