Circuit arrangement for suppressing CRT beam in television recei

Details Circuit arrangement for suppressing CRT beam in television recei Circuit arrangement for suppressing CRT beam in television recei

1979-09-06

1981-04-07

Blum, Theodore M.

Electric lamp and discharge devices: systems

Cathode ray tube circuits

Cathode-ray deflections circuits

315384, H01J 2952

Patent

active

042609356

ABSTRACT:
For the periodic suppression of the beam of a cathode-ray tube in a television receiver during flyback, in response to a blanking pulse V.sub.2 normally accompanied by a flyback pulse V.sub.1 of shorter duration, a control transistor T.sub.11 is saturated to render conductive a master transistor T.sub.7 in series therewith, together with several slave transistors T.sub.6, T.sub.8 and T.sub.13 forming current mirrors with transistor T.sub.7. Slave transistor T.sub.13 lies in series with a Zener diode DZ across which the beam-suppressing signal V.sub.3 is generated; slave transistor T.sub.6 activates a comparator CMP having an input A connected to a biasing circuit PL1 including slave transistor T.sub.8. Another input B of the comparator receives from a voltage divider PL2 a biasing voltage of such magnitude that an output C of the comparator feeds back a holding signal to another control transistor T.sub.12, in parallel with transistor T.sub.11, to maintain the conduction of master transistor T.sub.7 until a flyback pulse V.sub.1 applied to biasing circuit PL1 reverses the comparator whereby the beam-suppressing signal V.sub.3 disappears with the blanking pulse V.sub.2. In the absence of flyback pulse V.sub.1, signal V.sub.3 persists for an indefinite period.

REFERENCES:
patent: 4176301 (1979-11-01), Sonnenberger
Philips, Technical Note 078, TDA2652-Integrated Vertical Deflection for 30AX.

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