Circuit arrangement for setting a voltage supply for a test...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185250, C365S185230

Reexamination Certificate

active

06950358

ABSTRACT:
A circuit arrangement for setting a voltage supply for a test mode of an integrated memory contains a voltage generator circuit for generating a supply voltage to apply to bit lines of the memory. A control circuit is driven by a test mode signal for identifying a test mode and is connected to the voltage generator circuit. The control circuit enables the supply voltage to be applied to at least one of the bit lines in the test mode. The voltage generator circuit generates a negative supply voltage value in the test mode in order to carry out a burn-in test mode with a sufficiently high voltage difference between word line and bit line even in the case of small feature dimensions and at the same time to comply with voltage limits with regard to a snapback breakdown.

REFERENCES:
patent: 6049495 (2000-04-01), Hsu et al.
patent: 6549480 (2003-04-01), Hosogane et al.
patent: 6714065 (2004-03-01), Komiya et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Circuit arrangement for setting a voltage supply for a test... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit arrangement for setting a voltage supply for a test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit arrangement for setting a voltage supply for a test... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3434301

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.