Circuit arrangement for scalable output drivers

Details Circuit arrangement for scalable output drivers Circuit arrangement for scalable output drivers

2002-03-18

2003-07-22

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S102000

Reexamination Certificate

active

06597200

ABSTRACT:

The present invention relates to a circuit arrangement for scalable output drivers, and relates in particular to a circuit arrangement with symmetrical positioning of n- and p-channel transistors as output drivers.
Conventionally, a pair of n- and p-channel transistors is used in a driver arrangement in such a way that, in a manner dependent on an input voltage, an output voltage can be varied between a ground level and a plus voltage level of a voltage supply line. In accordance with an output power demand, the pair of driver transistors is designed as driver transistor group in such a way that a line width, i.e. a width of transistors as a dimension perpendicular to a source-drain path and parallel to an interconnect layer plane, is varied between the source terminal and the drain terminal from driver transistor group to driver transistor group. This line width is referred to as transistor line width below.
The driver transistors are embodied for example as field-effect transistors (FET), which are disclosed inter alia in “Johannes Lehmann: Feldeffekt-Transistoren [Field-effect transistors], Vogel-Verlag, ISBN 3-8023-0066-1 (pages 22-25)” and “U. Tietze and Ch. Schenk: Halbleiterschaltungstechnik [Semiconductor circuitry], 5th Edition, Springer-Verlag, ISBN 3-540-09848-8 (pages 77-91)”.
Such driver stages comprising a pair of n- and p-channel transistors are designed as transistor driver groups and are in many cases used as output drivers for electronic circuits (OCD=Off-Chip Driver). In this case, scalability of the output drivers is demanded in order to comply with different applications with regard to an output power, an output voltage, an output current, etc.
Scalability of a driver stage or of a driver transistor group can be achieved by effecting splitting into individual transistor pairs whose transistor line width is adjustable. If a plurality of transistor pairs having a different transistor line width are present, this results in unfavorable area utilization for circuit arrangements according to the prior art, since long, narrow geometrical forms are produced.
FIG. 3
shows a line driver according to the prior art, in which, by way of example, a driver transistor pair, comprising a p-channel transistor
104
and an n-channel transistor
105
, is connected to an output terminal unit
101
. In this case, the drain terminal of the p-channel transistor
104
is connected via a line to the output terminal unit, which is simultaneously connected to a drain terminal of the n-channel transistor
105
via a resistance element
103
.
The resistance element
103
serves to protect the n-channel transistor
105
against electrostatic discharges and the like. The source terminal of the n-channel transistor
105
is connected to a ground line
107
, while the source terminal of the p-channel transistor
104
is connected to a voltage supply line
106
, via which a supply voltage V
cc
is fed.
If a control signal is simultaneously fed to the gate terminal of the p-channel transistor
104
and to the gate terminal of the n-channel transistor
105
via a control line
108
, then it is possible to vary a voltage level of an output terminal unit
101
with regard to the ground line
107
and the voltage supply line
105
and thus to realize a driver function.
A further conventional circuit arrangement of an output driver using a transistor pair which forms a driver transistor group is shown in FIG.
4
. In this case, the two transistors
104
,
105
are arranged on both sides of an output terminal unit
101
. The line connections correspond to those shown in
FIG. 3
, i.e. simultaneous driving of the gate terminals of the two driver transistors
104
,
105
makes it possible to vary a potential of the output terminal unit
101
with regard to ground. It is also the case with the conventional circuit arrangement shown in
FIG. 3
that the two gate terminals must be connected to one another and to a control line, in this case there being the disadvantage, in particular, that the two gate terminals to be connected are arranged on opposite sides of the output terminal unit
101
.
One disadvantage of the conventional circuit arrangements for output drivers as shown by way of example in
FIGS. 3 and 4
is that scalability can be achieved only with a large area requirement.
A further disadvantage of conventional circuit arrangements is that line connections between the output terminal unit
101
and the corresponding driver transistors have different electrical properties. In the case of the arrangement shown in
FIG. 3
, the p-channel transistor
104
is located further away from the output terminal unit
101
than the n-channel transistor
105
. This different distance of the line connections leads to propagation time differences and hence to asymmetrical driving of the output driver.
The circuit arrangement shown in
FIG. 4
has the fundamental disadvantage that the p-channel transistor
104
and n-channel transistor
105
belonging to a pair of driver transistors lie on different sides of the output terminal unit
101
, resulting in very unfavorable area utilization.
Consequently, it is an object of the present invention to provide a circuit arrangement in which optimum area utilization is ensured and in which, moreover, as far as possible identical interconnect widths and interconnect lengths from the driver transistors to the output terminal unit are provided.
Scalability must be achieved in that, in the case of a higher output power demand (in the case of a higher voltage demand and/or in the case of a higher current demand), a transistor line width of driver transistors must be able to be increased, corresponding transistor line widths preferably differing by powers of 2.
The object of the present invention is achieved by means of a circuit arrangement according to claim
1
and a method according to claim
17
.
A main advantage of the invention is that the circuit arrangement according to the invention is symmetrical with regard to output interconnects and propagation time differences between corresponding driver transistors and an output terminal unit.
The drain terminals of the n- and p-channel transistors advantageously have identical electrical properties in the direction of the output terminal unit, thereby achieving, inter alia, strength in the circuit to withstand electrostatic discharges.
The driver arrangement is preferably scalable by implementing splitting into a suitable number of driver transistor groups, a driver transistor group being formed by a p-channel transistor and an n-channel transistor. Scalability can then be achieved in a simple manner in that individual driver transistor groups can be activated, whose transistor line width differs by powers of 2. Given four driver transistor groups, these are, for example, transistor line widths of B, B/2, B/4 and B/8.
In this way, the driver arrangement is subdivided into driver subunits. The total connection, i.e. the totality of all the output interconnects, is preferably split into individual connections, i.e. in each case two output interconnects for a driver transistor group comprising a p-channel transistor and an n-channel transistor.
A compact circuit arrangement is advantageously achieved, thereby ensuring optimum area utilization.
The transistors which form driver transistor groups are preferably combined in single p-channel units, single n-channel units, double n-channel units and double p-channel units.
The heart of the invention is a circuit arrangement for scalable output drivers, interconnects being arranged symmetrically between an output terminal unit and a driver transistor group comprising an n- and a p-channel transistor, and scalability being ensured in that in each case p-channel transistors and n-channel transistors are grouped in double n-channel units and double p-channel units.
Advantageous developments and improvements of the respective subject matter of the invention can be found in the subclaims.
In accordance with one preferred development of the present invention

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