Circuit arrangement for reading out, evaluating and reading...

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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C365S225700

Reexamination Certificate

active

07009900

ABSTRACT:
A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

REFERENCES:
patent: 4873668 (1989-10-01), Winnerl et al.
patent: 4916665 (1990-04-01), Atsumi et al.
patent: 5283761 (1994-02-01), Gillingham
patent: 5384730 (1995-01-01), Vinal
patent: 5696725 (1997-12-01), Kim
patent: 5748520 (1998-05-01), Asaka et al.
patent: 10233092 (1998-09-01), None

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